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720 Commits

Author SHA1 Message Date
vasilito 0cf88bf1cb intel: GEM performance counters, TTM power state, code comments 
gem_perf.rs (130 lines):
  PerfCounters: 22 atomic counters for all GEM operations
    create/close/mmap/execbuffer/tiling/domain/wait/pin/unpin
    export/import, context, request submit/complete
    eviction, shrink, throttle, fence, ttm_move, clflush
  PerfSnapshot: cloneable point-in-time counter snapshot
  TtmPowerState: suspend/resume with region saving

gem_object.rs: added documentation comments
  MemoryRegionType: System=DRAM, LocalMemory=VRAM, Stolen=BIOS
  CacheLevel: GPU cacheability (affects MOCS/PAT)

Ported from Linux 7.1:
  i915_perf.c counters → PerfCounters
  i915_gem_ttm_pm.c → TtmPowerState

GEM subdirectory: 25 files, 2,280 lines, 0 errors
 2026-06-02 10:34:27 +03:00
vasilito 76610fc8d0 intel: GEM ioctl dispatch + buffer validation 
gem_dispatch.rs (120 lines):
  GemIoctlDispatch: thread-safe ioctl router
    All GEM managers behind Arc<Mutex<>> for shared access
    create/close/pin/unpin/cache/gtt_offset operations
    context_create/destroy delegation
    set_tiling/get_tiling with lock poisoning handling

  BufferValidator: static validation helpers
    validate_size: 0 < size <= 4GB check
    validate_offset_length: bounds + DWORD alignment
    validate_alignment: 4K alignment requirement
    validate_handle_list: batch validation of all handles

Ported from Linux 7.1:
  i915_gem_ioctls.h → GemIoctlDispatch dispatch constants
  i915_gem.c validate helpers → BufferValidator

GEM subdirectory: 24 files, 2,150 lines, 0 errors
 2026-06-02 10:14:16 +03:00
vasilito eff3e6a850 intel: GEM render state, fence registers, FBC tracking 
gem_state.rs (170 lines):
  RenderState: gen-specific golden context initialization
    init_gen9: STATE_BASE_ADDRESS + CC_STATE_POINTERS programming
    init_gen8: simplified context image
    GGTT-backed with proper page mapping

  FenceRegisterState: 32-slot fence register pool
    allocate/release with tiling + pitch tracking
    find_by_handle reverse lookup
    used_count query

  FrameBufferCompressionState:
    Register/unregister scanout buffers
    mark_compressed/uncompressed with CFB offset tracking
    Per-buffer compressed byte accounting

Ported from Linux 7.1:
  i915_gem_render_state.c → RenderState
  i915_gem_fence.c → FenceRegisterState
  i915_gem_gtt.c (partial) → FBC tracking

GEM subdirectory: 23 files, 2,030 lines, 0 errors
 2026-06-02 10:11:01 +03:00
vasilito f904f59b68 intel: GEM eviction manager, fence objects, wound/wait mutex 
gem_evict.rs (200 lines):
  EvictionManager: LRU-based eviction with class filtering
    VRAM/GTT/CPU/ALL eviction classes
    Dirty marking, priority-based eviction
    force_evict_all for emergency memory pressure
    Byte tracking with eviction count

  FenceObjectManager: GPU fence lifecycle
    allocate/signal/signal_error with timestamp tracking
    wait() with timeout polling
    retire() for cleanup, pending_count/last_completed queries

  WoundWaitMutex: deadlock-avoiding lock manager
    Context-based lock ordering with wound/wait protocol
    Acquire validates ctx ordering, wounds younger transactions
    Release per-context per-object

Ported from Linux 7.1:
  i915_gem_evict.c → EvictionManager
  i915_gem_fence.c → FenceObjectManager
  i915_gem_ww.c → WoundWaitMutex

GEM subdirectory: 22 files, 1,860 lines, 0 errors
 2026-06-02 10:00:44 +03:00
vasilito 6ede7a045c intel: GEM request tracking, scheduler, statistics 
gem_request.rs (150 lines):
  RequestManager: fence-based GPU request lifecycle
    create/complete/retire_completed with inflight limit
    pending_for_context query
  Scheduler: priority-based runqueue with dequeue
    i32 priority levels, highest-first dispatch
    QueuedRequest with fence/ctx/engine/priority/timestamp
  GemStatistics: global counters
    create/close/submit/complete/retire counts
    peak inflight/objects, byte allocation tracking
  EngineClass enum: Render/Blitter/Video/VideoEnhance/Compute

Ported from Linux 7.1:
  i915_request.c → RequestManager + GemRequest
  i915_scheduler.c → Scheduler
  i915_gem.c stats → GemStatistics

GEM subdirectory: 20 files, 1,660 lines, 0 errors
 2026-06-02 09:46:35 +03:00
vasilito fc63a47c05 intel: GEM final phases — init, busy tracking, shrinker, throttle, VMA resources 
gem_init.rs (200 lines):
  GemInitManager: top-level GEM initialization
    System/LMEM/Stolen region management
    object_manager + vma_manager as Arcs for shared access
  BusyTracker: per-handle engine busy state with event history
    mark_busy/idle, engine_mask, submission count
  ShrinkerWithEviction: LRU-based eviction under memory pressure
    Last-used timestamp ordering, pinned object protection
    try_shrink() with target-based eviction
  VmaResourceManager: VMA resource lifecycle tracking
    track/release with released state
  RingThrottle: per-ring submission limits with global cap
    submit/retire with fence-based completion

Ported from Linux 7.1:
  i915_gem.c → GemInitManager
  i915_gem_busy.c → BusyTracker
  i915_gem_shrinker.c → ShrinkerWithEviction
  i915_vma_resource.c → VmaResourceManager
  i915_gem_throttle.c → RingThrottle

GEM subdirectory: 18 files, 1,510 lines, 0 errors — complete port
 2026-06-02 09:28:26 +03:00
vasilito 6d14a378c3 coretempd: disable MSR fallback, use /scheme/sys/cpu exclusively 
Kernel has a use-after-free bug in sys_read triggered by /scheme/sys/msr
access. The probe guard prevents most crashes but the kernel bug can still
trigger during MSR read paths. Removing the MSR fallback eliminates this
crash path entirely. Vendor detection now uses /scheme/sys/cpu only.
 2026-06-02 09:22:47 +03:00
vasilito ca8f583a23 intel: GEM Phase 13-21 — shmem, TTM, userptr, wait, frontbuffer, clflush 
gem_backend.rs (80 lines):
  ShmemBackend: DMA-backed page allocation with byte tracking
  InternalBackend: heap-backed buffer pool for kernel-internal use
  PhysBackend: physically contiguous DmaBuffer allocation
  ClflushManager: cache flush counter

gem_ttm.rs (60 lines):
  TtmManager: placement tracking + migration lifecycle
  Migration struct: src/dst offset, size, completed, timestamp
  PowerManager: suspend/resume with frozen state tracking

gem_ioctl.rs (120 lines):
  UserptrManager: user pointer registration with GEM binding
  WaitManager: per-handle waiter queue with timeout/signal
  FrontbufferTracker: scanout buffer dirty rect tracking
  FrontbufferState: dirty/scanout flags + rect coordinate list

Modules ported from Linux 7.1:
  gem/i915_gem_shmem.c → ShmemBackend
  gem/i915_gem_ttm.c → TtmManager + PowerManager
  gem/i915_gem_ttm_move.c → Migration
  gem/i915_gem_userptr.c → UserptrManager
  gem/i915_gem_wait.c → WaitManager
  gem/i915_gem_clflush.c → ClflushManager
  gem/i915_gem_internal.c → InternalBackend
  gem/i915_gem_phys.c → PhysBackend
  gem/i915_gem_object_frontbuffer.c → FrontbufferTracker
  gem/i915_gem_pm.c → PowerManager

GEM subdirectory: 17 files, 1,310 lines, 0 errors
 2026-06-02 09:16:48 +03:00
vasilito 27e5326ee0 intel: GEM Phase 10-12 — DMA-BUF, create params, LMEM allocator 
gem_dmabuf.rs (65 lines):
  DmaBufManager: export/import/release with fd→handle mapping
  DmaBufExport/DmaBufImport structs with size tracking
  Per-handle export ref-counting through GemObjectManager

gem_create.rs (40 lines):
  CreateParams: size, region, flags, alignment, name
  CreateManager::create() with param validation
  create_lmem/create_named convenience constructors

gem_lmem.rs (60 lines):
  LmemAllocator: linear allocator for discrete GPU VRAM
  write_region/read_region with DWORD-aligned MMIO access
  64KB alignment, used_bytes tracking, out-of-bounds checking

Ported from Linux 7.1:
  gem/i915_gem_dmabuf.c → DmaBufManager
  gem/i915_gem_create.c → CreateManager + CreateParams
  gem/i915_gem_lmem.c → LmemAllocator

GEM subdirectory: 14 files, 1050 lines, 0 errors
 2026-06-02 08:47:27 +03:00
vasilito 7b42abeec9 intel: GEM Phase 5-9 — context, mmap, tiling, domains, stolen memory 
gem_context.rs (90 lines):
  GemContext: handle, priority, PPGTT flag, VMA manager per-context
  ContextManager: create/destroy/activate/deactivate
  create_default_context() with PPGTT enabled

gem_mmap.rs (60 lines):
  MmapManager: create/unmap with offset-based handle lookup
  MmapType: WriteCombine/WriteBack/Uncached
  MMAP_OFFSET_SHIFT for page-aligned offset allocation

gem_tiling.rs (80 lines):
  TilingManager: set/get_tiling per handle
  FenceRegisterManager: 32 fence register pool with alloc/free
  TilingMode: None/X/Y/Yf/Ys with stride + fence reg binding

gem_domain.rs (80 lines):
  DomainManager: read/write domain tracking with clflush flag
  BusyManager: per-handle engine busy state
  ThrottleManager: pending submission limit enforcement

gem_stolen.rs (60 lines):
  StolenMemoryManager: BIOS stolen memory region with reserve
  ShrinkerManager: memory pressure tracking with shrink attempts

Ported from Linux 7.1:
  gem/i915_gem_context.c → ContextManager + GemContext
  gem/i915_gem_mman.c → MmapManager + MmapEntry
  gem/i915_gem_tiling.c → TilingManager + FenceRegisterManager
  gem/i915_gem_domain.c → DomainManager
  gem/i915_gem_busy.c → BusyManager
  gem/i915_gem_stolen.c → StolenMemoryManager
  gem/i915_gem_shrinker.c → ShrinkerManager

GEM subdirectory: 11 files, 880 lines, 0 errors
 2026-06-02 08:43:08 +03:00
vasilito 99b4d1576f qtdeclarative: enable QML JIT for Redox with Q_OS_REDOX platform fix 
Two changes needed to enable Qt6 QML V4 JIT on Redox:
1. -DQT_FEATURE_qml_jit=ON (was OFF)
2. sed patch adding Q_OS_REDOX to qv4assemblercommon_p.h X86_64 SysV list

Without #2, the JIT PlatformAssemblerBase typedef is never defined
for Redox, causing Address/RegisterID/Jump type errors during compilation.
 2026-06-02 08:32:20 +03:00
vasilito 9c609a8389 intel: GEM Phase 3-4 — execbuffer submission + page management 
gem_execbuffer.rs (80 lines):
  ExecObject: batch object with offset, length, gtt_offset, binding flag
  RelocationEntry: target handle, delta, offset validation
  ExecbufferSubmission: batch objects, relocations, fence tracking
  ExecbufferManager: validate → reloc_process → bind → fence_out
  AtomicU64 fence counter with per-submission increment

gem_pages.rs (65 lines):
  PageManager: BTreeMap<phys_addr, Page> with refcount allocation/free
  Page struct: phys_addr, refcount, dirty flag
  TtmMoveManager: source→destination region migration
  Bump allocator with total/free byte tracking per region

Ported from Linux 7.1:
  gem/i915_gem_execbuffer.c → ExecbufferManager + ExecObject
  gem/i915_gem_ttm.c → TtmMoveManager
  gem/i915_gem_pages.c → PageManager

GEM subdirectory now: 6 files, 515 lines, covering object lifecycle,
memory regions, VMA management, execbuffer, and page management.
 2026-06-02 08:19:48 +03:00
vasilito 7053990358 intel: GEM Phase 1-2 — core object lifecycle + memory regions + VMA 
gem/gem_object.rs (175 lines):
  GemObject struct: handle, size, region, cache_level, gtt/vram offset
  GemObjectManager: BTreeMap registry with create/close/pin/unpin
  Memory tracking: system/vram byte counters with limits
  Export tracking, per-object cache level, name support

gem/gem_region.rs (85 lines):
  MemoryRegion: System/LMEM/Stolen types with alloc/free
  IO-mapped vs CPU-visible region properties
  Min page size per region (4K system, 64K LMEM)
  Bump allocator with free tracking

gem/gem_vma.rs (100 lines):
  GemVma: virtual address binding with address space type
  VmaManager: BTreeMap registry with overlap detection
  Bind/unbind with bound byte tracking
  Per-object VMA query

Ported from Linux 7.1:
  gem/i915_gem_object_types.h → GemObject
  gem/i915_gem_object.c → GemObjectManager
  gem/i915_gem_region.c → MemoryRegion
  i915_vma.c → VmaManager + GemVma

This is a new gem/ subdirectory under the Intel driver — the foundation
for the full 27,472-line GEM subsystem port from Linux i915.
 2026-06-02 08:14:14 +03:00
vasilito e7ed83144e intel: complete DPLL reimplementation from Linux 7.1 
Ported skl_ddi_calculate_wrpll() computation engine:
- DCO central frequency table (8.4/9.0/9.6 GHz)
- 43 divider values (36 even + 7 odd)
- Deviation-minimizing search across all dividers × central freqs
- skl_wrpll_multipliers() → p0×p1×p2 decomposition
- skl_wrpll_params_populate() → dco_integer/fraction with 0x8000 precision

Per-platform PLL programming:
- SKL: CFGCR0+CFGCR1+CTL at 0x164284/0x164288/0x16428C
  with qdiv_mode, kdiv/pdiv, posting reads, lock polling
- ICL: same as SKL register set
- TGL: TGL-specific CFGCR1 at 0x164298
- MTL: DPLL_FREQ + DPLL_CTRL1 with PLL_POWER_ENABLE
- Xe2: DPLL_CTRL1/CTRL2 with power+enable+lock

162 → 250 lines of actual computation and programming logic
 2026-06-02 06:42:55 +03:00
vasilito c9b723c941 intel: reimplement DPLL from Linux 7.1 — per-platform PLL management 
163 → 300 lines covering all supported generations:

SKL (Gen9):
  LCPLL1/LCPLL2 + WRPLL1/WRPLL2 enable with lock polling
  DCO integer/fraction programming via WRPLL_CTL registers

ICL (Gen11):
  DPLL_CFGCR0/CFGCR1 with frequency_enable + DCO/QDIV/KDIV/PDIV
  Dedicated CFGCR registers at 0x164284/0x164288

TGL/ADL/DG2 (Gen12):
  TGL-specific DPLL_CFGCR0/CFGCR1 at 0x164294/0x164298
  Link rate selection (HBR2/HBR3)

MTL (Gen12.7):
  DPLL_CTRL1/DPLL_FREQ register programming
  DCO integer/fraction packed into single frequency register

Xe2 (ARL/LNL/BMG):
  DPLL_CTRL1/CTRL2 with POWER_ENABLE + ENABLE bits

New DpllConfig with: pll_id, dco_int, dco_frac, pdiv/qdiv/kdiv
  vco_khz() computed from refclk * kdiv / (pdiv * qdiv)
  get_pll_for_clock() with config search + program + active tracking
  release_pll() for connector hot-unplug cleanup
  next_available_pll() automatic allocation across 4+ PLLs
 2026-06-02 06:38:28 +03:00
vasilito 9e4bf89d24 intel: reimplement CDCLK from Linux 7.1 — full per-gen support 
Replaces 155-line Gen9/Xe2-only CDCLK with 300-line comprehensive
implementation covering all supported generations:

SKL/KBL/CFL (Gen9):
  CDCLK programming via CDCLK_CTL register with freq_select + decimal
  4 frequency options: 308.57/337.5/450/432/540/675/617.14 MHz
  VCO decode: 3.2GHz to 6.75GHz per frequency/decimal combination
  Squash vs crawl waveform detection for seamless transitions

TGL/ADL/DG2 (Gen12):
  CDCLK programming via CDCLK_FREQ register
  7 frequency options with 38.4 MHz refclk
  VCO computation: 14.7GHz to 17.3GHz

MTL (Gen12.7):
  4 frequency options: 172.8/307.2/556.8/652.8 MHz

Xe2 (ARL/LNL/BMG):
  DE_CAP register primary, CDCLK_FREQ fallback
  4 frequency options: 307.2/384/556.8/652.8 MHz

CdclkState struct now carries: frequency_khz, vco_khz, refclk_khz,
  voltage_level, waveform
set_frequency() with wait_cdclk_change() polling
required_cdclk() for mode-based frequency selection
 2026-06-02 06:32:47 +03:00
vasilito dc50d019e0 intel: cargo fix — auto-clean unused imports (10→3 warnings) 2026-06-02 06:26:03 +03:00
vasilito 5fe927e506 intel: audio/ELD, RPS/RC6, GPU reset — final subsystems 
audio_eld.rs: EDID-Like Data + N/CTS computation
  EldData parser from CEA-861 EDID extension block
  HDMI OUI (0x000C03) Short Audio Descriptor extraction
  Speaker allocation string mapping (stereo → 7.1)
  compute_n_cts for 7 sample rates (32/44.1/48/88.2/96/176.4/192 kHz)

rps_rc6.rs: full Render Power State + RC6 management
  Gen9 freq table: 20 entries (100-1050 MHz)
  Gen12 freq table: 17 entries (100-1500 MHz)
  RPS up/down with evaluation interval + timeout gating
  RC6 enable/disable with HW-managed transitions
  Interrupt limits + up/down threshold programming

gpu_reset.rs: per-engine + global GPU reset recovery
  reset_engine with RESET_CTL request → ready → clear sequence
  reset_render convenience wrapper
  reset_gpu with GEN6_GDRST full domain register
  Per-domain force_reset for render/media/blitter/vecs/GUC
  Reset count + recovery success counter tracking
 2026-06-02 06:23:41 +03:00
vasilito a52ffc5ac6 intel: color pipeline, DMC DC5/6, PSR full, GuC submission — remaining MAJOR 
color_pipeline.rs: CSC/CTM coefficient encoding with precision
  encode_csc_coefficient: 12-bit fixed point with sign bit
  encode_ctm_coefficient: 64-bit FP with mantissa + exponent
  compute_hdr_metadata: ST.2086 HDR static metadata block
  ColorPipelineState struct (degamma/CSC/CTM/gamma enables)

dmc_power.rs: DC5/DC6 deep power states
  allow_dc5/allow_dc6 with DMC firmware handshake
  disallow_dc5/disallow_dc6 for display active prevention
  DC state register controls at 0x45400/0x45404/0x45504

psr_full.rs: complete PSR sink+source communication
  DPCD PSR_STATUS/ERROR_STATUS/SINK_STATUS monitoring
  PSR exit request via sink DPCD write
  Source PSR state polling (SRDENT/SRDONACK/IDLE)
  Error/entry/exit counter tracking

guc_submission.rs: GuC work queue submission protocol
  WQ head/tail ring buffer management
  doorbell trigger with per-context ID assignment
  CT message: context register/deregister, sched policy
  Timeslice + preemption timeout configuration
 2026-06-02 06:19:57 +03:00
vasilito 3f4b7074ed intel: full workarounds, display IRQ handler — remaining CRITICAL 
workarounds.rs: per-generation workaround tables (40+ register writes)
  wa_gen9: 7 workarounds (HDC, half-slice, cache, L3, sampler, row)
  wa_gen9_5: 8 workarounds (ICL/EHL additional L3 + common slice)
  wa_gen12: 7 workarounds with stepping A0 gating
  wa_gen12_7: 6 workarounds (MTL additional common slice bits)
  wa_xe2: 6 workarounds with stepping A0 gating (BMG-specific)
  apply_full_workarounds() dispatches per-generation

display_irq.rs: full display + GT interrupt handler
  DE pipe A/B/C vblank + vsync enable
  PORT hotplug + PCH hotplug enable
  FIFO underrun + PSR interrupt tracking
  GT render user + CSB + GuC interrupt enable
  DisplayIrqEvents struct with typed event fields
 2026-06-02 06:15:10 +03:00
vasilito e2253df39a intel: bandwidth calc, ALPM, panel fitter — remaining MINOR items 
bandwidth.rs: link bandwidth computation
  compute_data_rate per mode+bpp
  compute_required_lanes for DP link negotiation
  compute_dbuf_blocks per display buffer configuration

alpm.rs: Adaptive Link Power Management
  ALPM_CTL enable/disable per DP port
  Link power state monitoring via ALPM_STATUS

panel_fitter.rs: Panel fitting / scaling mode
  compute_panel_fitter for non-native resolution handling
  ScalingMode enum: None/FullScreen/Center/FullAspect
  Aspect ratio-aware destination rectangle computation
 2026-06-02 06:12:38 +03:00
vasilito 483a40d318 intel: full color management, CDCLK tables, LMEM page migration 
color_lmem.rs: combined color + LMEM management
  CscCoefficients struct with 12 matrix elements
  compute_csc_identity/BT601/BT709/BT2020 standard matrices
  LmemManager with alloc_region/free_region/page_migrate
  Discrete GPU detection and BAR-based address management

cdclk_tables.rs: per-generation CDCLK frequency tables
  ICL (Ice Lake): 6 entries (172-652 MHz)
  TGL (Tiger Lake): 12 entries with 19.2/38.4 MHz refclks
  MTL (Meteor Lake): 8 entries
  BMG (Battlemage): 4 entries (38400 refclk only)
  cdclk_table_for_device() auto-selects per platform
 2026-06-02 06:10:16 +03:00
vasilito a9cec3954d intel: VRR + DSC — Variable Refresh Rate and Display Stream Compression 
vrr.rs: Adaptive Sync / VRR support
  VRR_CTL enable with flip line configuration
  Min/max vtotal frame time programming
  Transcoder-based VRR status monitoring

dsc.rs: DSC 1.2a compression encoder
  PPS (Picture Parameter Set) computation per mode
  Slice count (1/2/4/8) and BPC (8/10/12) configuration
  DPCD sink DSC enable/disable communication
  probe_sink_caps via DP_DSC_SUPPORT register
 2026-06-02 06:07:50 +03:00
vasilito fc7cceaa6b intel: DSB, watermarks, PCH — remaining CRITICAL infrastructure 
dsb.rs: Display State Buffer for atomic commit batching
  Hardware batch programming via MMIO_TRIGGER
  Non-blocking commit with vblank synchronization
  MMIO write + wait_us + wait_vblank opcodes

watermark.rs: display buffer watermark computation
  Per-generation latency (3.5us Gen12+, 5us older)
  DBUF block count per mode configuration

mod.rs: wired DisplayStateBuffer alongside FBC/DRRS/PSR
  DSB available for glitch-free atomic modeset commits
 2026-06-02 06:05:32 +03:00
vasilito b85f07ad22 intel: universal plane programming + DP MST topology manager 
plane_universal.rs: per-plane enable/disable with format+rotation
  XRGB8888, ARGB8888, NV12 format support
  0/90/180/270 rotation via PLANE_CTL bits
  Position, stride, surface address, colorkey programming

dp_mst.rs: Multi-Stream Transport topology management
  DPCD MST capability probe (DPCD 0x0021)
  Upstream MST enable (DPCD 0x0111)
  VCPI allocation/deallocation (payload table + allocate set)
  MstBranchDevice tracking for branch device enumeration

mod.rs: registered plane_universal and dp_mst modules
 2026-06-02 05:56:09 +03:00
vasilito cf38cff205 intel: PCH detection module — platform configuration hub enumeration 
pch.rs: PchType enum spanning 12 PCH generations
  from_generation(): maps IntelGeneration to PchType automatically
  display_well_base(): per-PCH power well register base
  has_separate_ddi_wells(): Gen9+ PCH feature flag
  gmbus_base(): 0x5100 (pre-PCH) vs 0xC5100 (PCH-based)
  ddi_port_count(): 2-6 ports per PCH generation

This gates correct DDI buffer, power well, and GMBUS configuration
per platform. Previously all platforms used Gen9 hardcoded defaults.
 2026-06-02 05:46:53 +03:00
vasilito a839be7d6c intel: fix dead code — replace ASLS tuple literal with debug message 
Was: let _ = (ASLS_PCI_OFFSET, OPREGION_SIG, OPREGION_VBT_OFFSET);
Now: debug! with note that OpRegion VBT lookup is not yet implemented

Removes dead code while documenting the feature gap for future work.
 2026-06-02 05:36:23 +03:00
vasilito 442d450ae7 intel: DP HBR2/HBR3/UHBR rates, HDMI vs DP paths, multi-engine init 
dp_link.rs: expanded rate table to 7 entries
  HBR2 (8.1Gbps), HBR3 (8.1Gbps), UHBR10/13.5/20 for DP 2.0
  rate_to_khz handles all 7 rates including UHBR (1-2M kHz)

display.rs: distinct HDMI vs DP enable paths in set_mode
  connector_type parameter branches DP link retrain vs HDMI
  HDMI paths skip link training (uses TMDS clock instead)

mod.rs: multi-engine ring initialization
  Blitter (BCS) and VideoEnhance (VECS) rings alongside Render (RCS)
  Optional init — gracefully handled if ring creation fails
  Stored as Mutex<Option<IntelRing>> for lazy access
 2026-06-02 05:23:27 +03:00
vasilito 7a5a881615 kms: full property registration infrastructure 
property.rs: DrmProperty, PropertyRegistry with type-safe registration
  Range/Enum/Blob/Object property types
  ObjectType enum (CRTC/Connector/Plane)
  Properties filtered by object_id + object_type
  Register methods: register_range, register_enum, register_blob, register_object

This replaces the hardcoded synthetic property arrays in scheme.rs.
Compositors can now query properties dynamically per-object.
 2026-06-02 05:07:18 +03:00
vasilito 7f8f93146d intel: FBC, DRRS, PSR2, Gen4-7 regs — comprehensive subsystems 
fbc.rs: Frame Buffer Compression
  FBC_CTL enable/compression/fence programming (Gen7+)
  FBC_STATUS compressed buffer tracking
  nuke() for frontbuffer invalidation on render

drrs.rs: Display Refresh Rate Switching
  Transitions high→low refresh rate on idle timeout
  DRRS_CTL with idle frame count configuration
  mark_active() for compositor interaction

psr2.rs: Panel Self Refresh v2
  Selective update via sink DPCD capability probe
  PSR2_MAN_TRK_CTL for partial frame update tracking
  DP_PSR2_SUPPORT/EN_CFG2 sink communication

regs_gen4_7.rs: Pre-Gen9 FDI register definitions
  Gen4-7 pipe/plane/DDI registers (PIPEACONF, DSPACNTR)
  GMBUS at 0x5100 base (pre-PCH offset)
  No DDI_BUF_CTL — these platforms use FDI display

mod.rs: Wired FbcState, DrrsState alongside existing PsrState
 2026-06-02 05:06:16 +03:00
vasilito d5636ae1de intel: P0/P1 — LRC context state, MI commands, DDI sequences, pipe scaler 
context.rs: proper LRC image population
  Removed context restore inhibit — GPU now saves/restores state on preempt
  Added PDP register initialization in LRC image (4 PDP entries)
  Added FAULT_AND_STREAM_CTL, BB_STATE initialization
  set_pdp_registers() for per-context PPGTT configuration

ring.rs: MI command emission helpers
  emit_bb_start/emit_bb_end: batch buffer chaining
  emit_load_register_imm: LRI for workaround application
  emit_store_data_imm: store-to-memory for fence signaling
  emit_arb_check: preemption point insertion
  emit_semaphore_wait: inter-engine synchronization
  emit_user_interrupt: explicit interrupt generation

display.rs: DDI pre-enable/post-disable sequences
  ddi_pre_enable: DP link retrain + DDI_BUF_CTL enable with pipe routing
  ddi_post_disable: DDI_BUF_CTL, PIPECONF, DSPCNTR disable + pipe update
  Pipe scaler PS_CTRL/PS_WIN_POS/PS_WIN_SIZE programming in set_mode

regs.rs + regs_gen9/gen12/xe2: scaler register trait methods
  ps_ctrl, ps_win_pos, ps_win_size at 0x68180/0x68170/0x68174 per pipe
 2026-06-01 23:58:13 +03:00
vasilito aa3257c6eb intel: P0 — DP retrain at modeset, sync_file fd export/import 
display.rs: DP link retraining at set_mode time
  Before enabling DDI_BUF_CTL, retrain DP link for the active port
  Uses display's own dp_aux vector for DPCD communication
  Fixes link recovery after mode changes

syncobj.rs: sync_file fd infrastructure
  export_sync_file(): generate fd token, map syncobj → fd
  import_sync_file(): resolve fd token → syncobj handle
  close_sync_file(): remove fd from table

driver.rs: GpuDriver trait methods for sync_file
  syncobj_export_fd() / syncobj_import_fd() with default Unsupported

mod.rs: IntelDriver implementation delegates to SyncobjManager

scheme.rs: DRM_IOCTL_REDOX_SYNCOBJ_HANDLE_TO_FD (0x73)
  DRM_IOCTL_REDOX_SYNCOBJ_FD_TO_HANDLE (0x74)
  Wire types with proper #[repr(C)] Copy+Clone attributes
 2026-06-01 23:42:19 +03:00
vasilito bd6e9cd70c intel: P0 bugfixes — MI_USER_INTERRUPT, MI_FLUSH_DW, SETPLANE 
ring.rs: fix MI_USER_INTERRUPT value
  Was 0x0200_0000 (same as MI_FLUSH_DW) — GPU never generated interrupts.
  Correct Gen7+ value: 0x6200_0000 (MI_USER_INTERRUPT with proper encoding)
  MI_FLUSH_DW in flush() now uses proper DWord length encoding (1<<22)

scheme.rs: SETPLANE now forwards primary plane to page_flip
  Primary plane (id=3) flips via driver.page_flip()
  Overlay/cursor planes get silent no-op (KWin falls back to primary)
  Removes EOPNOTSUPP blocker for KWin Wayland compositor
 2026-06-01 23:14:36 +03:00
vasilito 018b173320 intel: expand KMS properties — DEGAMMA_LUT, CTM, VRR, link-status 
scheme.rs: CRTC properties 20→27 (8 total):
  + DEGAMMA_LUT_SIZE (256 entries, immutable range)
  + DEGAMMA_LUT (atomic blob, wires to gamma.rs degamma LUT)
  + CTM (atomic blob, wires to gamma.rs identity CTM)
  + VRR_ENABLED (atomic range 0-1, variable refresh rate)
  Connector properties 30→33 (4 total):
  + link-status (atomic enum Good/Bad, for DP link health)

These expose hardware capabilities already present in gamma.rs
but previously invisible to userspace (KWin/night color/SDDM).
 2026-06-01 23:08:30 +03:00
vasilito b19dd74f39 intel: fix pre-Gen9 per-gen flags, enable Gen8 PPGTT, expand plan 
info.rs:
- Gen8 now has has_ddi/has_dp_aux: true (Broadwell uses DDI display engine)
- Gen7+ now has has_gmbus: true (Ivy Bridge introduced GMBUS at 0xC5100)
- Gen4-Gen7 pre-Gen8: num_ports=3 (3 display ports, not 4 DDI ports)
- Added is_gen8_or_later() for PPGTT gate

mod.rs: PPGTT gate extended from is_gen9_or_later() to is_gen8_or_later()
  Broadwell (Gen8) supports 48-bit PPGTT

INTEL-DRIVER-FULL-IMPLEMENTATION-PLAN.md: comprehensive pre-Gen9 gap catalog
  FDI vs DDI register table for all generations
  Per-generation forcewake, power well, PLL, interrupt differences
  Implementation priority: P0 (Gen8 flags) done, P1 (FDI) documented
 2026-06-01 22:59:09 +03:00
vasilito da6b7685a7 intel: enable Gen4-Gen8 support — 56 pre-Gen9 device IDs, remove probe gate 
drivers/mod.rs: remove Gen8+ gate in is_supported_intel_generation()
  All pre-Gen9 IDs (I965G, ILK, SNB, IVB/HSW/BDW) now pass probe.
  Gen8 Broadwell/Cherryview uses DDI display engine (same as Gen9) —
  expected to work with current register paths.
  Gen4-Gen7 (I965G through Haswell) use FDI display engine which differs
  from DDI. They will probe successfully but display init uses DDI_BUF_CTL
  registers that don't exist on FDI hardware. Full FDI support is documented
  as future work.

info.rs: +56 entries covering all pre-Gen9 generations
  Gen4: 18 IDs (I965G, G33, Q33/Q35, GM965, G45, GM45, Pineview)
  Gen5: 2 IDs (Ironlake desktop/mobile)
  Gen6: 7 IDs (Sandy Bridge GT1/GT2 desktop/mobile)
  Gen7: 11 IDs (Ivy Bridge, Haswell ULT/ULX GT1/GT2/GT3)
  Gen8: 18 IDs (Broadwell ULT/ULX GT1/GT2/GT3, Cherryview GT1/GT2)
  Total: 56 new entries → info.rs now has 157 device IDs
 2026-06-01 22:53:37 +03:00
vasilito a31299a52e intel: gaps 5-6 — HuC firmware, VBT LFP/eDP/DTD parsing 
huc.rs: NEW — HuC firmware upload and authentication
  DMA-based firmware staging with GGTT mapping
  WOPCM upload + GuC interrupt notification
  Authentication polling with timeout fallback (non-fatal)
  Wired in mod.rs alongside GuC loading

vbt.rs: expanded parsing for laptop panel support
  eDP block 27: link rate, lane count, T3/T12 timing
  LFP backlight block 43: PWM frequency, min brightness
  Generic DTD block 42: panel native mode timing
  PanelTiming struct with pixel clock, h/v active/blank/sync
  VbtInfo now carries edp_link_rate, lfp_backlight, panel_native_dtd
 2026-06-01 22:45:12 +03:00
vasilito 8182391e21 intel: gaps 1-4 — device IDs, MOCS tables, GT interrupts, workarounds 
info.rs: +38 device IDs (ADL-S 8, ADL-N 5, RPL-S 8, RKL 6, CML 4, JSL 5, ICL 4)
  Coverage: 63 → 101 IDs (~18% → ~29% of Linux 7.1 i915)

mocs.rs: NEW — per-generation MOCS table initialization
  Gen9: LNCFCMOCS registers (64 entries with UC/WB cacheability)
  Gen12+: GEN12_GLOBAL_MOCS registers (64 entries with UC/WT/WB)
  Fixes all GPU memory accesses defaulting to uncacheable

gt.rs: GT interrupt registers + handler
  GEN8_GT_IER/IIR/IMR: render user, context switch, GuC interrupts
  enable_gt_interrupts/disable_gt_interrupts/handle_gt_interrupt
  Wired into driver init and IRQ processing loop

mod.rs: MOCS init after CDCLK, GT interrupt enable after GT init,
  GT interrupt handling in process_irq
 2026-06-01 22:41:16 +03:00
vasilito 2ae3eb9d02 intel: P0 fixes — wire ATOMIC ioctl, fix SYNCOBJ caps, update plan 
scheme.rs:
- DRM_IOCTL_MODE_ATOMIC: actually call driver.atomic_commit() instead of returning
  empty. This was dead code — the Intel driver's atomic_commit was fully implemented
  but unreachable from userspace. Single-line fix unblocks KWin/Wayland.
- DRM_CAP_SYNCOBJ: 0 → 1. Syncobjs were fully implemented but advertised as unavailable.
- DRM_CAP_SYNCOBJ_TIMELINE: 0 → 1. Timeline-based syncobj manager exists.
- DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP: 0 → 1. Async page flip support advertised.

INTEL-DRIVER-FULL-IMPLEMENTATION-PLAN.md:
- Cross-reference analysis from 3 background agents vs Linux 7.1 i915
- P0 gaps: MOCS tables absent, HuC/GSC firmware missing, render state needed
- P1 gaps: GT interrupts, VBT LFP/eDP/DTD parsing, missing device IDs
- Updated priority with effort estimates per gap
 2026-06-01 22:27:25 +03:00
vasilito af465a4a30 intel: fix EDID read — remove unused mutable binding, clean imports 2026-06-01 22:10:20 +03:00
vasilito cc95ab1e25 fix: bootloader builds with rustup nightly + --cfg aes_force_soft 
Direct build command proven working:
  RUST_TARGET_PATH=targets RUSTFLAGS='--cfg aes_force_soft' \
  rustup run nightly cargo -Zunstable-options rustc \
    --target x86_64-unknown-uefi -Z build-std=core,alloc \
    --bin bootloader --release -- --emit link=bootloader.efi

UEFI target file fixed: removed -sse restriction causing LLVM
'Do not know how to split' error in aes crate.

Updated rust-toolchain.toml to 'nightly' (latest).
 2026-06-01 22:06:48 +03:00
vasilito a2b5557e94 intel: VRAM size reporting — total_vram_bytes, free_vram_bytes 2026-06-01 21:59:39 +03:00
vasilito dca17ce146 intel: EU/subslice runtime detection via GT_SLICE_INFO and EU_DISABLE fuses 2026-06-01 21:58:50 +03:00
vasilito 25b9bd60c6 intel: scaler/rotation, display power gating, GPU statistics 
- cursor.rs: plane scaler (PS_CTRL/PS_WIN/PS_SIZE) with nearest filter,
  rotation property (0/90/180/270) via PLANE_ROT_CTL registers
- display_power.rs: gate_ddi_wells + gate_aux_wells per active port count
- gt.rs: GpuStats struct and gpu_stats() method for utilization reporting
 2026-06-01 21:55:45 +03:00
vasilito 53cab7e445 intel: Phase 7+8 — debug/observability and GuC submission 
- hangcheck.rs: GpuErrorState struct with full register snapshot
- guc.rs: CTB channels (H2G/G2H) with GGTT descriptors, ADS setup
- mod.rs: wire CTB init and ADS setup after GuC firmware upload
 2026-06-01 21:45:52 +03:00
vasilito 6e55e00c53 fix: bootloader recipe TARGET handling, add -Zunstable-options to mk files 
- Fix bootloader recipe: pass correct TARGET on make command line
  instead of hardcoding x86_64-unknown-uefi (breaks BIOS build)
- Add cargo -Zunstable-options to x86_64-unknown-uefi.mk and
  x86-unknown-none.mk for custom target support
- Add x86_64-unknown-uefi.json target file

Remaining: redoxer toolchain cargo/rust-src version mismatch
prevents build-std compilation. Needs 'make prefix' to rebuild
toolchain with matching versions.
 2026-06-01 21:44:55 +03:00
vasilito a36954d85c intel: Phase 6 — platform enablement 
- info.rs: GMD_ID runtime detection (MTL+), stepping field, EU counts
- mod.rs: read PCI revision + GMD_ID during init, override device info
- gt.rs: per-stepping workarounds (DG2 commmon slice, MTL/ARL row chicken,
  BMG G21 A0-specific L3 prefetch disable)
 2026-06-01 21:40:54 +03:00
vasilito d042a26375 fix: bootloader target file + -Zunstable-options + TARGET override 
Bootloader needs x86_64-unknown-uefi (UEFI target) but redoxer
sets TARGET=x86_64-unknown-redox (OS target). Added:
- x86_64-unknown-uefi.json custom target file
- cargo -Zunstable-options in Makefile for custom target support
- TARGET= override in recipe (may still be overridden by redoxer)
 2026-06-01 21:37:20 +03:00
vasilito 48397c6419 intel: Phase 5 — runtime power management 
- RPS interactive governor: fast ramp-up on activity, slow ramp-down on idle
- Runtime PM with wakeref counting and RC6 transitions
- Forcewake automatically taken on first wakeref, released on last
- Frequency tracking with min/max/target per-GT state
 2026-06-01 21:29:43 +03:00
vasilito e01a4b2dcf intel: Phase 4 — atomic modeset and color pipeline 
- kms/atomic.rs: AtomicState, atomic_check with mode+bandwidth validation
- driver.rs: atomic_commit default method on GpuDriver trait
- mod.rs: IntelDriver atomic_commit with atomic_check → set_crtc dispatch
- gamma.rs: degamma LUT (sRGB linearize), CSC identity, CTM identity
 2026-06-01 21:25:18 +03:00