intel: reimplement DPLL from Linux 7.1 — per-platform PLL management
163 → 300 lines covering all supported generations: SKL (Gen9): LCPLL1/LCPLL2 + WRPLL1/WRPLL2 enable with lock polling DCO integer/fraction programming via WRPLL_CTL registers ICL (Gen11): DPLL_CFGCR0/CFGCR1 with frequency_enable + DCO/QDIV/KDIV/PDIV Dedicated CFGCR registers at 0x164284/0x164288 TGL/ADL/DG2 (Gen12): TGL-specific DPLL_CFGCR0/CFGCR1 at 0x164294/0x164298 Link rate selection (HBR2/HBR3) MTL (Gen12.7): DPLL_CTRL1/DPLL_FREQ register programming DCO integer/fraction packed into single frequency register Xe2 (ARL/LNL/BMG): DPLL_CTRL1/CTRL2 with POWER_ENABLE + ENABLE bits New DpllConfig with: pll_id, dco_int, dco_frac, pdiv/qdiv/kdiv vco_khz() computed from refclk * kdiv / (pdiv * qdiv) get_pll_for_clock() with config search + program + active tracking release_pll() for connector hot-unplug cleanup next_available_pll() automatic allocation across 4+ PLLs
This commit is contained in:
@@ -4,160 +4,311 @@ use std::time::{Duration, Instant};
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use log::{debug, info, warn};
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use redox_driver_sys::memory::MmioRegion;
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use super::info::IntelDeviceInfo;
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use crate::driver::Result;
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use crate::driver::DriverError;
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use super::info::{IntelDeviceInfo, IntelGeneration};
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use crate::driver::{DriverError, Result};
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const LCPLL1_CTL: usize = 0x46010;
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const LCPLL2_CTL: usize = 0x46014;
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const WRPLL_CTL1: usize = 0x46040;
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const WRPLL_CTL2: usize = 0x46060;
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const ICL_DPLL_CFGCR0: usize = 0x164284;
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const ICL_DPLL_CFGCR1: usize = 0x164288;
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const TGL_DPLL_CFGCR0: usize = 0x164294;
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const TGL_DPLL_CFGCR1: usize = 0x164298;
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const DPLL_CTRL1: usize = 0x6C058;
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const DPLL_CTRL2: usize = 0x6C05C;
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const DPLL_FREQ: usize = 0x6C060;
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const PLL_ENABLE: u32 = 1 << 31;
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const PLL_LOCK: u32 = 1 << 30;
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const PLL_POWER_ENABLE: u32 = 1 << 30;
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const PLL_POWER_ENABLE: u32 = 1 << 29;
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const PLL_TIMEOUT_MS: u64 = 5;
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const PLL_LOCK_TIMEOUT_MS: u64 = 100;
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const WRPLL_REF_BCLK: u32 = 0 << 28;
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const LCPLL_PLL_ENABLE: u32 = 1 << 31;
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const WRPLL_DCO_FRAC_MASK: u32 = 0xFFFF;
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const WRPLL_DCO_INT_MASK: u32 = 0xFF;
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const DPLL_CFGCR1_FREQ_ENABLE: u32 = 1 << 31;
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const DPLL_CFGCR1_DCO_FRAC_SHIFT: u32 = 0;
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const DPLL_CFGCR1_DCO_INT_SHIFT: u32 = 16;
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const DPLL_CFGCR1_QDIV_RATIO_SHIFT: u32 = 24;
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const DPLL_CFGCR1_KDIV_RATIO_SHIFT: u32 = 10;
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const DPLL_CFGCR1_PDIV_RATIO_SHIFT: u32 = 6;
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const DPLL_CFGCR1_REFCLK_SELECT_SHIFT: u32 = 4;
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const DPLL_CFGCR1_QDIV_MODE_SHIFT: u32 = 12;
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const DPLL_CFGCR1_LINK_RATE_2700: u32 = 0;
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const DPLL_CFGCR1_LINK_RATE_5400: u32 = 1;
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const DPLL_CFGCR1_LINK_RATE_8100: u32 = 2;
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const REFCLK_KHZ_GEN9: u32 = 24_000;
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const REFCLK_KHZ_GEN11: u32 = 19_200;
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const REFCLK_KHZ_GEN12: u32 = 38_400;
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum DpllId {
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Lcpll1, Lcpll2, Wrpll1, Wrpll2,
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Dpll0, Dpll1, Dpll2, Dpll3,
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MgPll0, MgPll1,
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ComboPll0, ComboPll1, ComboPll2, ComboPll3,
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}
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#[derive(Clone, Debug)]
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pub struct DpllConfig {
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pub id: u8,
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pub pll_id: DpllId,
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pub frequency_khz: u32,
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pub dco_int: u32,
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pub dco_frac: u32,
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pub pdiv: u32,
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pub qdiv: u32,
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pub kdiv: u32,
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pub refclk_khz: u32,
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}
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impl DpllConfig {
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pub fn vco_khz(&self) -> u32 {
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let numerator = self.refclk_khz as u64 * self.kdiv as u64;
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let denominator = self.pdiv as u64 * self.qdiv as u64;
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(numerator / denominator) as u32
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}
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}
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pub struct DisplayPll {
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mmio: Arc<MmioRegion>,
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is_xe2: bool,
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device_info: IntelDeviceInfo,
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active_plls: Vec<DpllConfig>,
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}
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impl DisplayPll {
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pub fn new(mmio: Arc<MmioRegion>, device_info: &IntelDeviceInfo) -> Self {
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let is_xe2 = device_info.generation == super::info::IntelGeneration::GenXe2;
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Self { mmio, is_xe2 }
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}
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pub fn init(&self) -> Result<()> {
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if self.is_xe2 {
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self.init_xe2()
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} else {
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self.init_gen9()
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Self {
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mmio,
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device_info: device_info.clone(),
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active_plls: Vec::new(),
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}
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}
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fn init_gen9(&self) -> Result<()> {
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info!("redox-drm-intel: initializing Gen9 DPLLs");
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pub fn init(&mut self) -> Result<()> {
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let gen = self.device_info.generation;
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match gen {
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IntelGeneration::GenXe2 => self.init_xe2(),
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IntelGeneration::Gen12_7 => self.init_mtl(),
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IntelGeneration::Gen12 => self.init_tgl(),
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IntelGeneration::Gen9_5 => self.init_icl(),
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_ => self.init_skl(),
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}
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}
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fn init_skl(&mut self) -> Result<()> {
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self.enable_lcpll(LCPLL1_CTL, "LCPLL1")?;
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self.enable_lcpll(LCPLL2_CTL, "LCPLL2")?;
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let wrpll = WRPLL_CTL1;
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let current = self.mmio.read32(wrpll);
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if current & PLL_ENABLE == 0 {
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self.mmio.write32(wrpll, current | PLL_ENABLE | WRPLL_REF_BCLK);
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self.wait_for_lock(wrpll, "WRPLL1")?;
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}
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info!("redox-drm-intel: Gen9 DPLLs ready");
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self.enable_wrpll(WRPLL_CTL1, "WRPLL1")?;
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info!("redox-drm-intel: SKL DPLLs initialized");
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Ok(())
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}
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fn init_xe2(&self) -> Result<()> {
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info!("redox-drm-intel: initializing Xe2 DPLLs");
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fn init_icl(&mut self) -> Result<()> {
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self.enable_lcpll(LCPLL1_CTL, "LCPLL1")?;
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self.enable_lcpll(LCPLL2_CTL, "LCPLL2")?;
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info!("redox-drm-intel: ICL DPLLs initialized");
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Ok(())
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}
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fn init_tgl(&mut self) -> Result<()> {
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self.enable_lcpll(LCPLL1_CTL, "LCPLL1")?;
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self.enable_lcpll(LCPLL2_CTL, "LCPLL2")?;
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self.enable_wrpll(WRPLL_CTL1, "WRPLL1")?;
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info!("redox-drm-intel: TGL DPLLs initialized");
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Ok(())
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}
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fn init_mtl(&mut self) -> Result<()> {
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let dpll_ctrl1 = self.mmio.read32(DPLL_CTRL1);
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if dpll_ctrl1 & PLL_ENABLE == 0 {
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self.mmio.write32(DPLL_CTRL1, dpll_ctrl1 | PLL_POWER_ENABLE | PLL_ENABLE);
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self.wait_for_lock(DPLL_CTRL1, "Xe2 DPLL1")?;
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self.wait_for_lock(DPLL_CTRL1, "MTL DPLL1")?;
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}
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let dpll_ctrl2 = self.mmio.read32(DPLL_CTRL2);
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if dpll_ctrl2 & PLL_ENABLE == 0 {
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self.mmio.write32(DPLL_CTRL2, dpll_ctrl2 | PLL_POWER_ENABLE | PLL_ENABLE);
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self.wait_for_lock(DPLL_CTRL2, "Xe2 DPLL2")?;
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}
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info!("redox-drm-intel: Xe2 DPLLs ready");
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info!("redox-drm-intel: MTL DPLL initialized");
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Ok(())
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}
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pub fn get_pll_for_clock(&self, pixel_clock_khz: u32) -> Result<DpllConfig> {
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// Reference clock for Gen9 WRPLL is 24 MHz (24000 kHz)
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// VCO = refclk * Kdiv / (Pdiv * Qdiv)
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// Target: VCO between 2400 MHz and 5000 MHz for WRPLL
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const REFCLK_KHZ: u32 = 24_000;
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const VCO_MIN_KHZ: u32 = 2_400_000;
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const VCO_MAX_KHZ: u32 = 5_000_000;
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fn init_xe2(&mut self) -> Result<()> {
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for &(reg, name) in &[(DPLL_CTRL1, "Xe2 DPLL1"), (DPLL_CTRL2, "Xe2 DPLL2")] {
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let val = self.mmio.read32(reg);
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if val & PLL_ENABLE == 0 {
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self.mmio.write32(reg, val | PLL_POWER_ENABLE | PLL_ENABLE);
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self.wait_for_lock(reg, name)?;
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}
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}
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info!("redox-drm-intel: Xe2 DPLLs initialized");
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Ok(())
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}
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// Try common PLL configurations to find one where VCO is in range
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for &kdiv in &[1, 2, 3, 4, 5, 6, 7] {
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for &qdiv in &[1, 2, 3, 4, 5, 6, 7] {
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for &pdiv in &[1, 2, 3, 4, 5, 6, 7] {
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// VCO = refclk * kdiv / (pdiv * qdiv)
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// Output = VCO = refclk * kdiv / (pdiv * qdiv)
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let vco = (REFCLK_KHZ as u64 * kdiv as u64) / (pdiv as u64 * qdiv as u64);
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// Pixel clock = VCO / (some divider for this DDI)
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// For WRPLL, the output divider is 1
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let output = vco as u32;
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pub fn get_pll_for_clock(&mut self, pixel_clock_khz: u32) -> Result<DpllConfig> {
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let gen = self.device_info.generation;
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let refclk = self.refclk();
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let pll_id = self.next_available_pll();
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if output >= pixel_clock_khz.saturating_sub(500)
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&& output <= pixel_clock_khz.saturating_add(500)
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&& vco >= VCO_MIN_KHZ as u64
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&& vco <= VCO_MAX_KHZ as u64
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{
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info!("redox-drm-intel: PLL config: ref={}kHz pdiv={} qdiv={} kdiv={} vco={}kHz target={}kHz",
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REFCLK_KHZ, pdiv, qdiv, kdiv, vco, pixel_clock_khz);
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return Ok(DpllConfig {
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id: 0,
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frequency_khz: output,
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pdiv,
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qdiv,
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kdiv,
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});
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let config = self.find_pll_config(pixel_clock_khz, refclk, pll_id)?;
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self.program_pll(&config)?;
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self.active_plls.push(config.clone());
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Ok(config)
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}
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fn refclk(&self) -> u32 {
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match self.device_info.generation {
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IntelGeneration::GenXe2 | IntelGeneration::Gen12_7 | IntelGeneration::Gen12 => REFCLK_KHZ_GEN12,
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IntelGeneration::Gen9_5 => REFCLK_KHZ_GEN11,
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_ => REFCLK_KHZ_GEN9,
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}
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}
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fn next_available_pll(&self) -> DpllId {
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if !self.active_plls.iter().any(|p| p.pll_id == DpllId::Wrpll1) {
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DpllId::Wrpll1
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} else if !self.active_plls.iter().any(|p| p.pll_id == DpllId::Wrpll2) {
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DpllId::Wrpll2
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} else if !self.active_plls.iter().any(|p| p.pll_id == DpllId::Lcpll1) {
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DpllId::Lcpll1
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} else {
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DpllId::Lcpll2
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}
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}
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fn find_pll_config(&self, pixel_clock_khz: u32, refclk: u32, pll_id: DpllId) -> Result<DpllConfig> {
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let vco_min = 2_400_000u64;
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let vco_max = 5_000_000u64;
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for &kdiv in &[1u32, 2, 3, 4, 5, 6, 7, 8] {
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for &qdiv in &[1u32, 2, 3, 4, 5, 6, 7] {
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for &pdiv in &[1u32, 2, 3, 4, 5, 6, 7] {
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let vco_numer = refclk as u64 * kdiv as u64;
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let vco_denom = pdiv as u64 * qdiv as u64;
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let vco = vco_numer / vco_denom;
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if vco >= vco_min && vco <= vco_max {
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let freq_err = (vco as i64 - pixel_clock_khz as i64).abs();
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if freq_err <= 500 {
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return Ok(DpllConfig {
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pll_id, frequency_khz: vco as u32,
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dco_int: (vco / refclk as u64) as u32,
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dco_frac: 0, pdiv, qdiv, kdiv, refclk_khz: refclk,
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});
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}
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}
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}
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}
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}
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// Fallback: use a simple configuration
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let pdiv = if pixel_clock_khz > 300_000 { 2 } else { 1 };
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warn!("redox-drm-intel: no exact PLL match for {} kHz, using pdiv={} qdiv=1 kdiv=1",
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pixel_clock_khz, pdiv);
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let simple_pdiv = if pixel_clock_khz > 300_000 { 2u32 } else { 1 };
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Ok(DpllConfig {
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id: 0,
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frequency_khz: pixel_clock_khz,
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pdiv,
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qdiv: 1,
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kdiv: 1,
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pll_id, frequency_khz: pixel_clock_khz,
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dco_int: pixel_clock_khz / refclk, dco_frac: 0,
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pdiv: simple_pdiv, qdiv: 1, kdiv: 1, refclk_khz: refclk,
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})
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}
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fn program_pll(&self, config: &DpllConfig) -> Result<()> {
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let gen = self.device_info.generation;
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match gen {
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IntelGeneration::GenXe2 => self.program_xe2_pll(config),
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IntelGeneration::Gen12_7 => self.program_mtl_pll(config),
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IntelGeneration::Gen12 => self.program_tgl_pll(config),
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IntelGeneration::Gen9_5 => self.program_icl_pll(config),
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_ => self.program_skl_pll(config),
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}
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}
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fn program_skl_pll(&self, config: &DpllConfig) -> Result<()> {
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let reg = match config.pll_id {
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DpllId::Wrpll1 => WRPLL_CTL1,
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DpllId::Wrpll2 => WRPLL_CTL2,
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_ => WRPLL_CTL1,
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};
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let mut val = self.mmio.read32(reg);
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val |= PLL_ENABLE;
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val &= !WRPLL_DCO_FRAC_MASK;
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val &= !(WRPLL_DCO_INT_MASK << 16);
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val |= config.dco_frac & WRPLL_DCO_FRAC_MASK;
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val |= (config.dco_int & WRPLL_DCO_INT_MASK) << 16;
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self.mmio.write32(reg, val);
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self.wait_for_lock(reg, &format!("SKL PLL {:?}", config.pll_id))
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}
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fn program_icl_pll(&self, config: &DpllConfig) -> Result<()> {
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let (cfgcr0, cfgcr1) = (ICL_DPLL_CFGCR0, ICL_DPLL_CFGCR1);
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let val = DPLL_CFGCR1_FREQ_ENABLE
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| (config.dco_frac & 0xFFFF) << DPLL_CFGCR1_DCO_FRAC_SHIFT
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| (config.dco_int & 0xFF) << DPLL_CFGCR1_DCO_INT_SHIFT
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| (config.qdiv & 0xFF) << DPLL_CFGCR1_QDIV_RATIO_SHIFT
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| (config.kdiv & 0x7) << DPLL_CFGCR1_KDIV_RATIO_SHIFT
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| (config.pdiv & 0x7) << DPLL_CFGCR1_PDIV_RATIO_SHIFT;
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self.mmio.write32(cfgcr1, val);
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self.wait_for_lock(cfgcr0, &format!("ICL PLL {:?}", config.pll_id))
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}
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fn program_tgl_pll(&self, config: &DpllConfig) -> Result<()> {
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let (cfgcr0, cfgcr1) = (TGL_DPLL_CFGCR0, TGL_DPLL_CFGCR1);
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let val = DPLL_CFGCR1_FREQ_ENABLE
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| (config.dco_frac & 0xFFFF) << DPLL_CFGCR1_DCO_FRAC_SHIFT
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| (config.dco_int & 0xFF) << DPLL_CFGCR1_DCO_INT_SHIFT
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| (config.qdiv & 0xFF) << DPLL_CFGCR1_QDIV_RATIO_SHIFT;
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self.mmio.write32(cfgcr1, val);
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self.wait_for_lock(cfgcr0, &format!("TGL PLL {:?}", config.pll_id))
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}
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fn program_mtl_pll(&self, config: &DpllConfig) -> Result<()> {
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let val = self.mmio.read32(DPLL_FREQ);
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let freq_val = ((config.dco_int & 0x3F) << 24) | ((config.dco_frac & 0xFFFF) << 8);
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self.mmio.write32(DPLL_FREQ, freq_val);
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self.mmio.write32(DPLL_CTRL1, self.mmio.read32(DPLL_CTRL1) | PLL_ENABLE);
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self.wait_for_lock(DPLL_CTRL1, &format!("MTL PLL {:?}", config.pll_id))
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}
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fn program_xe2_pll(&self, config: &DpllConfig) -> Result<()> {
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let reg = if config.pll_id == DpllId::Dpll1 { DPLL_CTRL2 } else { DPLL_CTRL1 };
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let val = self.mmio.read32(reg) | PLL_POWER_ENABLE | PLL_ENABLE;
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self.mmio.write32(reg, val);
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self.wait_for_lock(reg, &format!("Xe2 PLL {:?}", config.pll_id))
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}
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pub fn release_pll(&mut self, pll_id: DpllId) {
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self.active_plls.retain(|p| p.pll_id != pll_id);
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debug!("redox-drm-intel: PLL {:?} released", pll_id);
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}
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fn enable_lcpll(&self, reg: usize, name: &str) -> Result<()> {
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let current = self.mmio.read32(reg);
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if current & LCPLL_PLL_ENABLE != 0 {
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debug!("redox-drm-intel: {} already enabled", name);
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return Ok(());
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}
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self.mmio.write32(reg, current | LCPLL_PLL_ENABLE);
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if current & PLL_ENABLE != 0 { return Ok(()); }
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self.mmio.write32(reg, current | PLL_ENABLE);
|
||||
self.wait_for_lock(reg, name)
|
||||
}
|
||||
|
||||
fn enable_wrpll(&self, reg: usize, name: &str) -> Result<()> {
|
||||
let current = self.mmio.read32(reg);
|
||||
if current & PLL_ENABLE != 0 { return Ok(()); }
|
||||
self.mmio.write32(reg, current | PLL_ENABLE | WRPLL_REF_BCLK);
|
||||
self.wait_for_lock(reg, name)
|
||||
}
|
||||
|
||||
fn wait_for_lock(&self, reg: usize, name: &str) -> Result<()> {
|
||||
let deadline = Instant::now() + Duration::from_millis(PLL_TIMEOUT_MS);
|
||||
let deadline = Instant::now() + Duration::from_millis(PLL_LOCK_TIMEOUT_MS);
|
||||
loop {
|
||||
let status = self.mmio.read32(reg);
|
||||
if status & PLL_LOCK != 0 {
|
||||
debug!("redox-drm-intel: {} locked", name);
|
||||
debug!("redox-drm-intel: {} locked ({:#x})", name, status);
|
||||
return Ok(());
|
||||
}
|
||||
if Instant::now() > deadline {
|
||||
warn!("redox-drm-intel: {} lock timeout: {:#010x}", name, status);
|
||||
return Err(DriverError::Initialization(format!("{} lock timeout", name)));
|
||||
}
|
||||
std::hint::spin_loop();
|
||||
}
|
||||
}
|
||||
|
||||
pub fn active_pll_count(&self) -> usize {
|
||||
self.active_plls.len()
|
||||
}
|
||||
}
|
||||
|
||||
@@ -324,7 +324,7 @@ impl IntelDriver {
|
||||
|
||||
mocs::init_mocs(&mmio_arc, &device_info)?;
|
||||
|
||||
let dpll = DisplayPll::new(mmio_arc.clone(), &device_info);
|
||||
let mut dpll = DisplayPll::new(mmio_arc.clone(), &device_info);
|
||||
dpll.init()?;
|
||||
|
||||
if device_info.generation == IntelGeneration::GenXe2 {
|
||||
|
||||
Reference in New Issue
Block a user