intel: P0 bugfixes — MI_USER_INTERRUPT, MI_FLUSH_DW, SETPLANE

ring.rs: fix MI_USER_INTERRUPT value
  Was 0x0200_0000 (same as MI_FLUSH_DW) — GPU never generated interrupts.
  Correct Gen7+ value: 0x6200_0000 (MI_USER_INTERRUPT with proper encoding)
  MI_FLUSH_DW in flush() now uses proper DWord length encoding (1<<22)

scheme.rs: SETPLANE now forwards primary plane to page_flip
  Primary plane (id=3) flips via driver.page_flip()
  Overlay/cursor planes get silent no-op (KWin falls back to primary)
  Removes EOPNOTSUPP blocker for KWin Wayland compositor
This commit is contained in:
2026-06-01 23:14:36 +03:00
parent 018b173320
commit bd6e9cd70c
2 changed files with 11 additions and 5 deletions
@@ -27,7 +27,7 @@ const RING_CTL_SIZE_MASK: u32 = !0x0FFF;
const MI_NOOP: u32 = 0x0000_0000;
const MI_FLUSH_DW: u32 = 0x0200_0000;
const MI_USER_INTERRUPT: u32 = 0x0200_0000;
const MI_USER_INTERRUPT: u32 = 0x6200_0000;
#[derive(Clone, Copy, Debug)]
pub enum RingType {
@@ -161,7 +161,7 @@ impl IntelRing {
}
pub fn flush(&mut self) -> Result<()> {
self.submit_batch(&[MI_FLUSH_DW, MI_NOOP])
self.submit_batch(&[MI_FLUSH_DW | (1 << 22), 0x0000_0000])
}
pub fn has_activity(&mut self) -> Result<bool> {
@@ -1810,9 +1810,15 @@ impl DrmScheme {
}
DRM_IOCTL_MODE_SETPLANE => {
let _req = decode_wire::<DrmSetPlaneWire>(payload)?;
warn!("redox-drm: SETPLANE not implemented (hardware overlay/cursor planes require DC)");
return Err(Error::new(EOPNOTSUPP));
let req = decode_wire::<DrmSetPlaneWire>(payload)?;
if req.plane_id == PRIMARY_PLANE_ID && req.fb_id != 0 {
self.driver.page_flip(req.crtc_id, req.fb_id, 0)
.map_err(driver_to_syscall)?;
Vec::new()
} else {
debug!("redox-drm: SETPLANE ignored (overlay/cursor plane {})", req.plane_id);
Vec::new()
}
}
DRM_IOCTL_MODE_ADDFB => {