intel: P0 bugfixes — MI_USER_INTERRUPT, MI_FLUSH_DW, SETPLANE
ring.rs: fix MI_USER_INTERRUPT value Was 0x0200_0000 (same as MI_FLUSH_DW) — GPU never generated interrupts. Correct Gen7+ value: 0x6200_0000 (MI_USER_INTERRUPT with proper encoding) MI_FLUSH_DW in flush() now uses proper DWord length encoding (1<<22) scheme.rs: SETPLANE now forwards primary plane to page_flip Primary plane (id=3) flips via driver.page_flip() Overlay/cursor planes get silent no-op (KWin falls back to primary) Removes EOPNOTSUPP blocker for KWin Wayland compositor
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@@ -27,7 +27,7 @@ const RING_CTL_SIZE_MASK: u32 = !0x0FFF;
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const MI_NOOP: u32 = 0x0000_0000;
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const MI_FLUSH_DW: u32 = 0x0200_0000;
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const MI_USER_INTERRUPT: u32 = 0x0200_0000;
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const MI_USER_INTERRUPT: u32 = 0x6200_0000;
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#[derive(Clone, Copy, Debug)]
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pub enum RingType {
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@@ -161,7 +161,7 @@ impl IntelRing {
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}
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pub fn flush(&mut self) -> Result<()> {
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self.submit_batch(&[MI_FLUSH_DW, MI_NOOP])
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self.submit_batch(&[MI_FLUSH_DW | (1 << 22), 0x0000_0000])
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}
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pub fn has_activity(&mut self) -> Result<bool> {
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@@ -1810,9 +1810,15 @@ impl DrmScheme {
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}
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DRM_IOCTL_MODE_SETPLANE => {
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let _req = decode_wire::<DrmSetPlaneWire>(payload)?;
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warn!("redox-drm: SETPLANE not implemented (hardware overlay/cursor planes require DC)");
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return Err(Error::new(EOPNOTSUPP));
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let req = decode_wire::<DrmSetPlaneWire>(payload)?;
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if req.plane_id == PRIMARY_PLANE_ID && req.fb_id != 0 {
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self.driver.page_flip(req.crtc_id, req.fb_id, 0)
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.map_err(driver_to_syscall)?;
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Vec::new()
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} else {
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debug!("redox-drm: SETPLANE ignored (overlay/cursor plane {})", req.plane_id);
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Vec::new()
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}
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}
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DRM_IOCTL_MODE_ADDFB => {
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