Files
RedBear-OS/local/recipes
vasilito 3f4b7074ed intel: full workarounds, display IRQ handler — remaining CRITICAL
workarounds.rs: per-generation workaround tables (40+ register writes)
  wa_gen9: 7 workarounds (HDC, half-slice, cache, L3, sampler, row)
  wa_gen9_5: 8 workarounds (ICL/EHL additional L3 + common slice)
  wa_gen12: 7 workarounds with stepping A0 gating
  wa_gen12_7: 6 workarounds (MTL additional common slice bits)
  wa_xe2: 6 workarounds with stepping A0 gating (BMG-specific)
  apply_full_workarounds() dispatches per-generation

display_irq.rs: full display + GT interrupt handler
  DE pipe A/B/C vblank + vsync enable
  PORT hotplug + PCH hotplug enable
  FIFO underrun + PSR interrupt tracking
  GT render user + CSB + GuC interrupt enable
  DisplayIrqEvents struct with typed event fields
2026-06-02 06:15:10 +03:00
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