intel: full workarounds, display IRQ handler — remaining CRITICAL

workarounds.rs: per-generation workaround tables (40+ register writes) wa_gen9: 7 workarounds (HDC, half-slice, cache, L3, sampler, row) wa_gen9_5: 8 workarounds (ICL/EHL additional L3 + common slice) wa_gen12: 7 workarounds with stepping A0 gating wa_gen12_7: 6 workarounds (MTL additional common slice bits) wa_xe2: 6 workarounds with stepping A0 gating (BMG-specific) apply_full_workarounds() dispatches per-generation display_irq.rs: full display + GT interrupt handler DE pipe A/B/C vblank + vsync enable PORT hotplug + PCH hotplug enable FIFO underrun + PSR interrupt tracking GT render user + CSB + GuC interrupt enable DisplayIrqEvents struct with typed event fields
2026-06-02 06:15:10 +03:00
parent e2253df39a
commit 3f4b7074ed
2 changed files with 234 additions and 0 deletions
@@ -0,0 +1,121 @@
+use std::sync::Arc;
+use std::time::{Duration, Instant};
+
+use log::{debug, error, info, warn};
+use redox_driver_sys::memory::MmioRegion;
+
+use crate::driver::{DriverError, Result};
+
+const GEN8_GT_IER: usize = 0x4400C;
+const GEN8_GT_IIR: usize = 0x44008;
+const GEN8_GT_IMR: usize = 0x44010;
+const GT_RENDER_USER_INTERRUPT: u32 = 1 << 0;
+const GT_CSB_INTERRUPT: u32 = 1 << 16;
+const GT_GUC_INTERRUPT: u32 = 1 << 17;
+
+const DE_IER: usize = 0x44410;
+const DE_IMR: usize = 0x4440C;
+const DE_IIR: usize = 0x44408;
+const DE_PORT_ISR: usize = 0x44400;
+const DE_PIPEA_VBLANK: u32 = 1 << 7;
+const DE_PIPEA_VSYNC: u32 = 1 << 6;
+const DE_PIPEB_VBLANK: u32 = 1 << 15;
+const DE_PIPEB_VSYNC: u32 = 1 << 14;
+const DE_PIPEC_VBLANK: u32 = 1 << 23;
+const DE_PIPEC_VSYNC: u32 = 1 << 22;
+const DE_PORT_HOTPLUG: u32 = 1 << 4;
+const DE_PCH_HOTPLUG: u32 = 1 << 5;
+const DE_FIFO_UNDERRUN: u32 = 1 << 3;
+const DE_PSR_INTERRUPT: u32 = 1 << 27;
+
+pub struct DisplayIrqHandler {
+    mmio: Arc<MmioRegion>,
+    vblank_count: u64,
+    hotplug_count: u32,
+    psr_count: u32,
+    fifo_underrun_count: u32,
+}
+
+impl DisplayIrqHandler {
+    pub fn new(mmio: Arc<MmioRegion>) -> Self {
+        Self {
+            mmio,
+            vblank_count: 0,
+            hotplug_count: 0,
+            psr_count: 0,
+            fifo_underrun_count: 0,
+        }
+    }
+
+    pub fn enable_all(&self) {
+        let ier_val = DE_PIPEA_VBLANK | DE_PIPEA_VSYNC
+            | DE_PIPEB_VBLANK | DE_PIPEB_VSYNC
+            | DE_PIPEC_VBLANK | DE_PIPEC_VSYNC
+            | DE_PORT_HOTPLUG | DE_PCH_HOTPLUG
+            | DE_FIFO_UNDERRUN | DE_PSR_INTERRUPT;
+
+        let ier = self.mmio.read32(DE_IER);
+        self.mmio.write32(DE_IER, ier | ier_val);
+        self.mmio.write32(DE_IMR, self.mmio.read32(DE_IMR) & !ier_val);
+
+        info!("redox-drm-intel: display IRQs enabled (IER={:#x})", ier | ier_val);
+    }
+
+    pub fn disable_all(&self) {
+        let mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PIPEC_VBLANK
+            | DE_PORT_HOTPLUG | DE_FIFO_UNDERRUN;
+        self.mmio.write32(DE_IMR, self.mmio.read32(DE_IMR) | mask);
+    }
+
+    pub fn handle(&mut self) -> DisplayIrqEvents {
+        let iir = self.mmio.read32(DE_IIR);
+        if iir == 0 { return DisplayIrqEvents::default(); }
+
+        self.mmio.write32(DE_IIR, iir);
+
+        let mut events = DisplayIrqEvents::default();
+
+        if iir & (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PIPEC_VBLANK) != 0 {
+            self.vblank_count += 1;
+            events.vblank = true;
+        }
+        if iir & (DE_PORT_HOTPLUG | DE_PCH_HOTPLUG) != 0 {
+            self.hotplug_count += 1;
+            events.hotplug = true;
+        }
+        if iir & DE_PSR_INTERRUPT != 0 {
+            self.psr_count += 1;
+            events.psr = true;
+        }
+        if iir & DE_FIFO_UNDERRUN != 0 {
+            self.fifo_underrun_count += 1;
+            events.fifo_underrun = true;
+        }
+
+        events
+    }
+
+    pub fn enable_gt_interrupts(&self) {
+        let mask = GT_RENDER_USER_INTERRUPT | GT_CSB_INTERRUPT | GT_GUC_INTERRUPT;
+        let ier = self.mmio.read32(GEN8_GT_IER);
+        self.mmio.write32(GEN8_GT_IER, ier | mask);
+        self.mmio.write32(GEN8_GT_IMR, self.mmio.read32(GEN8_GT_IMR) & !mask);
+    }
+
+    pub fn handle_gt_interrupt(&self) -> u32 {
+        let iir = self.mmio.read32(GEN8_GT_IIR);
+        if iir != 0 {
+            self.mmio.write32(GEN8_GT_IIR, iir);
+            debug!("redox-drm-intel: GT interrupt IIR={:#x}", iir);
+        }
+        iir
+    }
+}
+
+#[derive(Default)]
+pub struct DisplayIrqEvents {
+    pub vblank: bool,
+    pub hotplug: bool,
+    pub psr: bool,
+    pub fifo_underrun: bool,
+}
@@ -0,0 +1,113 @@
+use std::sync::Arc;
+use std::time::{Duration, Instant};
+
+use log::{debug, info, warn};
+use redox_driver_sys::memory::MmioRegion;
+
+use super::info::{IntelDeviceInfo, IntelGeneration};
+use crate::driver::{DriverError, Result};
+use crate::kms::ModeInfo;
+
+pub fn apply_full_workarounds(mmio: &MmioRegion, device_info: &IntelDeviceInfo) -> u32 {
+    let mut count: u32 = 0;
+    let gen = device_info.generation;
+    let stepping = device_info.stepping;
+
+    info!("redox-drm-intel: applying full workarounds for {:?} stepping={}", gen, stepping);
+
+    count += wa_gen9(mmio, gen);
+    count += wa_gen9_5(mmio, gen);
+    count += wa_gen12(mmio, gen, stepping);
+    count += wa_gen12_7(mmio, gen);
+    count += wa_xe2(mmio, gen, stepping);
+
+    info!("redox-drm-intel: {} workarounds applied", count);
+    count
+}
+
+fn wa_gen9(mmio: &MmioRegion, gen: IntelGeneration) -> u32 {
+    if !matches!(gen, IntelGeneration::Gen9) { return 0; }
+    let mut c: u32 = 0;
+
+    let val = mmio.read32(0xE4F0); mmio.write32(0xE4F0, val | (1 << 4)); c += 1;
+    let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
+    let cm0 = mmio.read32(0x7000); mmio.write32(0x7000, cm0 | (1 << 3)); c += 1;
+    let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
+    let l3cfg = mmio.read32(0xB11C);
+    mmio.write32(0xB11C, l3cfg | (1 << 2)); c += 1;
+    mmio.write32(0xA0, 0x0080_0080 | (1 << 0)); c += 1;
+    let row_ch = mmio.read32(0xE4F0);
+    mmio.write32(0xE4F0, row_ch | (1 << 11)); c += 1;
+
+    c
+}
+
+fn wa_gen9_5(mmio: &MmioRegion, gen: IntelGeneration) -> u32 {
+    if !matches!(gen, IntelGeneration::Gen9_5) { return 0; }
+    let mut c: u32 = 0;
+
+    let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
+    let cm0 = mmio.read32(0x7000); mmio.write32(0x7000, cm0 | (1 << 3)); c += 1;
+    let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
+    let csc2 = mmio.read32(0x55B0); mmio.write32(0x55B0, csc2 | (1 << 9)); c += 1;
+    let l3cfg = mmio.read32(0xB11C); mmio.write32(0xB11C, l3cfg | (1 << 8)); c += 1;
+    let row_ch = mmio.read32(0xE4F0);
+    mmio.write32(0xE4F0, row_ch | (1 << 4) | (1 << 11)); c += 1;
+    mmio.write32(0xA0, 0x0080_0080 | (1 << 0)); c += 1;
+
+    c
+}
+
+fn wa_gen12(mmio: &MmioRegion, gen: IntelGeneration, stepping: u8) -> u32 {
+    if !matches!(gen, IntelGeneration::Gen12) { return 0; }
+    let mut c: u32 = 0;
+
+    let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
+    let l3cfg = mmio.read32(0xB11C); mmio.write32(0xB11C, l3cfg | (1 << 8)); c += 1;
+    let csc2 = mmio.read32(0x55B0); mmio.write32(0x55B0, csc2 | (1 << 9) | (1 << 12)); c += 1;
+    let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
+    let row_ch = mmio.read32(0xE4F0);
+    mmio.write32(0xE4F0, row_ch | (1 << 4) | (1 << 11)); c += 1;
+
+    if stepping == 0 {
+        let chk = mmio.read32(0x7300); mmio.write32(0x7300, chk | (1 << 8)); c += 1;
+    }
+
+    let cache_mode_0 = mmio.read32(0x7000);
+    mmio.write32(0x7000, cache_mode_0 | (1 << 3)); c += 1;
+
+    c
+}
+
+fn wa_gen12_7(mmio: &MmioRegion, gen: IntelGeneration) -> u32 {
+    if !matches!(gen, IntelGeneration::Gen12_7) { return 0; }
+    let mut c: u32 = 0;
+
+    let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
+    let l3cfg = mmio.read32(0xB11C); mmio.write32(0xB11C, l3cfg | (1 << 8)); c += 1;
+    let csc2 = mmio.read32(0x55B0); mmio.write32(0x55B0, csc2 | (1 << 9) | (1 << 12) | (1 << 15)); c += 1;
+    let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
+    let row_ch = mmio.read32(0xE4F0);
+    mmio.write32(0xE4F0, row_ch | (1 << 4) | (1 << 11)); c += 1;
+
+    c
+}
+
+fn wa_xe2(mmio: &MmioRegion, gen: IntelGeneration, stepping: u8) -> u32 {
+    if !matches!(gen, IntelGeneration::GenXe2) { return 0; }
+    let mut c: u32 = 0;
+
+    let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
+    let l3cfg = mmio.read32(0xB11C); mmio.write32(0xB11C, l3cfg | (1 << 8) | (1 << 16)); c += 1;
+    let csc2 = mmio.read32(0x55B0);
+    mmio.write32(0x55B0, csc2 | (1 << 9) | (1 << 12) | (1 << 15) | (1 << 18)); c += 1;
+    let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
+    let row_ch = mmio.read32(0xE4F0);
+    mmio.write32(0xE4F0, row_ch | (1 << 4) | (1 << 11)); c += 1;
+
+    if stepping == 0 {
+        let chk = mmio.read32(0x7300); mmio.write32(0x7300, chk | (1 << 8) | (1 << 16)); c += 1;
+    }
+
+    c
+}