intel: comprehensive workaround tables v2.0 — GT + context + display + engine + whitelist

Complete rewrite of workaround infrastructure:

- regs_gt.rs: 100+ GT/engine register constants with field bit masks
  for Gen4-Gen12 (L3, slice/row chicken, cache/sampler/WM, HSW,
  MCR selector, GAM/ECO, Gen11/Gen12, display WA registers)
- Workaround/WorkaroundList data model with merge/dedup at same offset,
  apply() with masked-register and write-only support, verify()
  for post-application validation
- Helper functions: wa_masked_en/dis/field_set, wa_write/or/clr/clr_set,
  MCR variants (aliases without MCR steering infrastructure)

Tables ported from Linux 7.1 intel_workarounds.c:
- GT workarounds: gen4, g4x, ilk, snb, ivb, hsw, gen8, gen9,
  icl(gen9.5), gen12 (~30 entries, all critical paths)
- Context workarounds: gen6, gen7, gen8, gen9, icl, gen12
  (~40 entries covering RCS/engine state)
- Display workarounds: gen11 (Wa_14010594013), gen12 (Wa_14013723622)
- Engine workarounds: general_render_compute (2 entries)
- Whitelist: gen9, icl, gen12 (17 entries total)

Total: ~90 workaround entries across 5 domains (GT/context/display/
engine/whitelist), 0 compilation errors.

Note: Engine-specific tables (rcs/xcs/ccs per-engine init) and full
Gen9 sub-family platform-specific entries (skl/bxt/kbl/glk/cfl stepping
variants) remain as follow-up work. The infrastructure supports them
fully — they just need register constant resolution and porting.

local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs

@@ -548,6 +548,35 @@ fn gen12_whitelist_build(wal: &mut WorkaroundList) {
     wa_add(wal, 0x7008, 0, 0, 0, "GEN12_CACHE_MODE_1");
 }
 
+// ---------------------------------------------------------------------------
+// Display workaround tables (from intel_display_wa.c)
+// ---------------------------------------------------------------------------
+
+pub fn build_display_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList {
+    let mut wal = WorkaroundList::new("display");
+    let gen = device_info.generation;
+
+    info!("redox-drm-intel: building display workarounds for {:?}", gen);
+
+    match gen {
+        IntelGeneration::Gen9_5 => gen11_display_wa_init(&mut wal),
+        IntelGeneration::Gen12 => gen12_display_wa_init(&mut wal),
+        _ => {}
+    }
+
+    wal
+}
+
+fn gen11_display_wa_init(wal: &mut WorkaroundList) {
+    /* Wa_14010594013:icl */
+    wa_masked_en(wal, GEN8_CHICKEN_DCPR_1, ICL_DELAY_PMRSP, "Wa_14010594013");
+}
+
+fn gen12_display_wa_init(wal: &mut WorkaroundList) {
+    /* Wa_14013723622:tgl */
+    wa_write_clr(wal, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, "Wa_14013723622");
+}
+
 // ---------------------------------------------------------------------------
 // Legacy top-level function kept for compatibility with existing driver init.
 // ---------------------------------------------------------------------------
@@ -556,11 +585,13 @@ pub fn apply_full_workarounds(mmio: &MmioRegion, device_info: &IntelDeviceInfo)
     let gt_wal = build_gt_workarounds(device_info);
     let ctx_wal = build_ctx_workarounds(device_info);
     let eng_wal = build_engine_workarounds(device_info);
+    let disp_wal = build_display_workarounds(device_info);
 
     let mut count = 0u32;
     count += gt_wal.apply(mmio).unwrap_or(0);
     count += ctx_wal.apply(mmio).unwrap_or(0);
     count += eng_wal.apply(mmio).unwrap_or(0);
+    count += disp_wal.apply(mmio).unwrap_or(0);
 
     info!("redox-drm-intel: {} total workarounds applied", count);
     count