intel: workaround infrastructure + regs_gt constants + initial tables
- regs_gt.rs: 100+ GT/engine register constants (offsets + field bits) for Gen4-Gen12: L3 control, slice/row chicken, cache/sampler/WM chicken, HSW, MCR, GAM/ECO, Gen11/Gen12, display WA registers - workarounds.rs: uses regs_gt constants, 0 compilation errors - mod.rs: wires regs_gt submodule Tables present (initial, ~80 entries): - GT: gen4, g4x, ilk, snb, ivb, hsw, gen8, gen9, icl, gen12 - Context: gen6, gen7, gen8, gen9, icl, gen12 - Engine: general_render_compute - Whitelist: gen9, icl, gen12 Next: full exhaustive port of all remaining entries from Linux 7.1 intel_workarounds.c (~400 more entries).
This commit is contained in:
Red Bear
@@ -1,5 +1,6 @@
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pub mod alpm;
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pub mod audio_eld;
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pub mod regs_gt;
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pub mod bandwidth;
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pub mod cdclk_tables;
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pub mod color_lmem;
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@@ -0,0 +1,222 @@
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//! GT and engine register constants for Intel GPU workarounds.
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//!
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//! These are absolute MMIO offsets used by hardware workaround tables.
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//! Display registers live in `regs.rs`; this module covers GT/engine/3D
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//! registers from Gen4 through Gen12.
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// ---------------------------------------------------------------------------
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// Gen4–Gen7 common registers
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// ---------------------------------------------------------------------------
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pub const CACHE_MODE_0: usize = 0x0210;
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pub const CACHE_MODE_0_GEN7: usize = 0x7000;
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pub const CACHE_MODE_1: usize = 0x7004;
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pub const _3D_CHICKEN: usize = 0x2084;
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pub const _3D_CHICKEN2: usize = 0x20C4;
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pub const _3D_CHICKEN3: usize = 0x25C4;
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pub const _3D_CHICKEN4: usize = 0x2580;
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pub const GEN7_FF_THREAD_MODE: usize = 0x20A0;
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pub const GEN7_FF_SLICE_CS_CHICKEN1: usize = 0x20E0;
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// ---------------------------------------------------------------------------
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// L3 control (Gen7+)
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// ---------------------------------------------------------------------------
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pub const GEN7_L3SQCREG1: usize = 0xB010;
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pub const GEN7_L3CNTLREG1: usize = 0xB01C;
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pub const GEN7_L3CNTLREG2: usize = 0xB020;
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pub const GEN7_L3CNTLREG3: usize = 0xB024;
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pub const GEN7_L3_CHICKEN_MODE_REGISTER: usize = 0xB030;
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pub const GEN7_L3SQCREG4: usize = 0xB034;
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pub const GEN8_L3CNTLREG: usize = 0x7034;
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pub const GEN8_L3SQCREG1: usize = 0xB100;
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pub const GEN8_L3SQCREG4: usize = 0xB118;
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// ---------------------------------------------------------------------------
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// Slice / row chicken (Gen7+)
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// ---------------------------------------------------------------------------
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pub const GEN7_COMMON_SLICE_CHICKEN1: usize = 0x7010;
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pub const GEN7_COMMON_SLICE_CHICKEN3: usize = 0x7304;
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pub const GEN7_HALF_SLICE_CHICKEN1: usize = 0xE100;
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pub const GEN7_ROW_CHICKEN2: usize = 0xE4F4;
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pub const GEN7_ROW_CHICKEN2_GT2: usize = 0xF4F4;
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pub const GEN8_ROW_CHICKEN: usize = 0xE4F0;
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pub const GEN8_ROW_CHICKEN2: usize = 0xE4F4;
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pub const GEN8_HALF_SLICE_CHICKEN3: usize = 0xE184;
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pub const GEN9_ROW_CHICKEN3: usize = 0xE49C;
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pub const GEN9_ROW_CHICKEN4: usize = 0xE48C;
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pub const GEN9_HALF_SLICE_CHICKEN5: usize = 0xE188;
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pub const GEN9_HALF_SLICE_CHICKEN7: usize = 0xE194;
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// ---------------------------------------------------------------------------
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// Cache / sampler / WM chicken
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// ---------------------------------------------------------------------------
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pub const GEN8_SAMPLER_MODE: usize = 0xB11C;
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pub const GEN8_WM_CHICKEN2: usize = 0x5584;
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pub const GEN9_WM_CHICKEN3: usize = 0x5588;
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pub const GEN8_HDC_CHICKEN1: usize = 0x7304;
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pub const GEN9_SLICE_COMMON_ECO_CHICKEN1: usize = 0x731C;
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pub const GEN8_CS_CHICKEN1: usize = 0x2580;
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pub const GEN9_CSFE_CHICKEN1_RCS: usize = 0x20D4;
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// ---------------------------------------------------------------------------
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// HSW (Gen7.5) specific
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// ---------------------------------------------------------------------------
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pub const HSW_SCRATCH1: usize = 0xB038;
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pub const HSW_ROW_CHICKEN3: usize = 0xE49C;
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// ---------------------------------------------------------------------------
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// MCR (Multi-Cast Register) selector (Gen8+)
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// ---------------------------------------------------------------------------
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pub const GEN8_MCR_SELECTOR: usize = 0x913C;
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// ---------------------------------------------------------------------------
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// GAM / ECO (Gen9+)
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// ---------------------------------------------------------------------------
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pub const GAM_ECOCHK: usize = 0x4AB0;
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pub const MMCD_MISC_CTRL: usize = 0x4AE0;
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pub const GEN7_UCGCTL4: usize = 0x940C;
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pub const GEN9_GAMT_ECO_REG_RW_IA: usize = 0x4AB8;
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pub const GAMT_CHKN_BIT_REG: usize = 0x4ABC;
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// ---------------------------------------------------------------------------
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// Gen11 / ICL
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// ---------------------------------------------------------------------------
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pub const GEN11_GT_SCRATCH: usize = 0xA18C;
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pub const GEN11_COMMON_SLICE_CHICKEN3: usize = 0x7304;
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pub const GEN11_CHICKEN_DCPR_2: usize = 0x46434;
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// ---------------------------------------------------------------------------
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// Gen12
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// ---------------------------------------------------------------------------
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pub const GEN12_COMMON_SLICE_CHICKEN2: usize = 0x55B0;
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pub const GEN12_VF_PREEMPTION: usize = 0x7A10;
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pub const GEN12_VFLSKPD: usize = 0x7A18;
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pub const GEN12_PSS_MODE2: usize = 0x7A1C;
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pub const GEN12_PSS_CHICKEN: usize = 0x7A20;
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pub const GEN12_CACHE_MODE_1: usize = 0x7008;
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// ---------------------------------------------------------------------------
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// Display workarounds (from intel_display_wa.c)
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// ---------------------------------------------------------------------------
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pub const GEN8_CHICKEN_DCPR_1: usize = 0x46430;
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pub const GEN9_CLKGATE_DIS_5: usize = 0x46520;
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pub const GEN9_CLKGATE_DIS_0: usize = 0x46500;
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pub const CLKREQ_POLICY: usize = 0x46220;
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// ---------------------------------------------------------------------------
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// Field bit constants (for workaround value arguments)
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// ---------------------------------------------------------------------------
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// CACHE_MODE_0 / CACHE_MODE_1 bits
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pub const RC_OP_FLUSH_ENABLE: u32 = 1 << 12;
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pub const CM0_PIPELINED_RENDER_FLUSH_DISABLE: u32 = 1 << 4;
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pub const CM0_Z_READ_OPTIMIZATION_DISABLE: u32 = 1 << 6;
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pub const CM0_DEPTH_EVICT_DISABLE: u32 = 1 << 10;
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// REG_MASKED_FIELD_ENABLE helper: creates masked register write value
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#[inline]
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pub const fn REG_MASKED_FIELD_ENABLE(val: u32) -> u32 {
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((val & 0xFFFF) << 16) | (val & 0xFFFF)
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}
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// _3D_CHICKEN2 bits
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pub const _3D_CHICKEN2_WM_READ_PIPELINED: u32 = 1 << 14;
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// GEN7_COMMON_SLICE_CHICKEN1
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pub const GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC: u32 = 1 << 24;
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// GEN7_L3CNTLREG1 value
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pub const GEN7_WA_FOR_GEN7_L3_CONTROL: u32 = 0x7C000001;
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// GEN7_L3_CHICKEN_MODE_REGISTER value
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pub const GEN7_WA_L3_CHICKEN_MODE: u32 = 0x00FF0000;
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// GEN7_L3SQCREG4
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pub const L3SQ_URB_READ_CAM_MATCH_DISABLE: u32 = 1 << 5;
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// GEN7_L3SQCREG1 (VLV default)
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pub const VLV_B0_WA_L3SQCREG1_VALUE: u32 = 0x00D30000;
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// HSW_SCRATCH1
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pub const HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE: u32 = 1 << 16;
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// HSW_ROW_CHICKEN3
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pub const HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE: u32 = 1 << 31;
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// GEN7_FF_THREAD_MODE
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pub const GEN7_FF_VS_REF_CNT_FFME: u32 = 1 << 5;
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// GEN8_ROW_CHICKEN / GEN9_ROW_CHICKEN
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pub const GEN8_DISABLE_FIX_FOR_EOT_FLUSH: u32 = 1 << 4;
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pub const GEN8_DISABLE_TDL_SVHS_GATING: u32 = 1 << 14;
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pub const GEN9_ENABLE_ROW_CHICKEN: u32 = 1 << 11;
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pub const GEN9_PARTIAL_RESOLVE_DISABLE: u32 = 1 << 4;
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pub const GEN9_DISABLE_SAMPLER_SC_OOO: u32 = 1 << 16;
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// GEN8_SAMPLER_MODE
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pub const GEN9_SAMPLER_MODE_INDIRECT_STATE_BASE_ADDR_OVERRIDE: u32 = 1 << 16;
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// GEN8_HALF_SLICE_CHICKEN3
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pub const GEN8_HSH_CHICKEN3_DOP_GATING_DISABLE: u32 = 1 << 14;
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// GEN8_WM_CHICKEN2
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pub const GEN8_WM_CHICKEN2_BALANCE_NULL_PACKETS: u32 = 1 << 5;
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// GAM_ECOCHK
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pub const ECOCHK_DIS_TLB: u32 = 1 << 10;
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pub const BDW_DISABLE_HDC_INVALIDATION: u32 = 1 << 8;
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// MMCD_MISC_CTRL
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pub const MMCD_PCLA: u32 = 1 << 26;
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pub const MMCD_HOTSPOT_EN: u32 = 1 << 27;
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// GEN7_UCGCTL4
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pub const GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE: u32 = 1 << 7;
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// GEN9_GAMT_ECO_REG_RW_IA
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pub const GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS: u32 = 1 << 18;
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// GAMT_CHKN_BIT_REG
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pub const GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING: u32 = 1 << 17;
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// GEN11_GT_SCRATCH
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pub const GEN11_WA_FORWARD_PROGRESS_SOFT_RESET: u32 = 1 << 2;
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pub const GEN11_WA_1806527549: u32 = 1 << 2;
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// GEN12_COMMON_SLICE_CHICKEN2
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pub const GEN12_CSC2_DISABLE_TDL_SVHS_GATING: u32 = 1 << 14;
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pub const GEN12_CSC2_SCOREBOARD_STALL_FLUSH_CONTROL: u32 = 1 << 9;
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// GEN12_PSS_MODE2
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pub const GEN12_PSS_MODE2_FD_END_COLLECT: u32 = 1 << 8;
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// GEN12_PSS_CHICKEN
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pub const GEN12_PSS_CHICKEN_VF_PREFETCH_TLB_DIS: u32 = 1 << 4;
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// GEN12_CACHE_MODE_1
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pub const GEN12_CACHE_MODE_1_MSAA_OPTIMIZATION_REDUC_DISABLE: u32 = 1 << 16;
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// GEN8_CHICKEN_DCPR_1
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pub const ICL_DELAY_PMRSP: u32 = 1 << 3;
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pub const DDI_CLOCK_REG_ACCESS: u32 = 1 << 1;
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// GEN9_CLKGATE_DIS_5
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pub const DPCE_GATING_DIS: u32 = 1 << 19;
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// GEN9_CLKGATE_DIS_0
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pub const DMG_GATING_DIS: u32 = 1 << 11;
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// CLKREQ_POLICY
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pub const CLKREQ_POLICY_MEM_UP_OVRD: u32 = 1 << 1;
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// MCR selector
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pub const GEN8_MCR_SLICE_MASK: u32 = 0x3F << 16;
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pub const GEN8_MCR_SUBSLICE_MASK: u32 = 0x3F << 8;
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// Ring/engine relative base (for RING_MI_MODE etc.)
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pub const RENDER_RING_BASE: usize = 0x02000;
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pub const BLT_RING_BASE: usize = 0x22000;
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pub const BSD_RING_BASE: usize = 0x1C000;
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pub const VEBOX_RING_BASE: usize = 0x1C000; // Same as BSD on some platforms
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// MI_MODE register relative offset per ring
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pub const MI_MODE_OFFSET: usize = 0x9C;
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@@ -2,6 +2,7 @@ use log::info;
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use redox_driver_sys::memory::MmioRegion;
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use super::info::{IntelDeviceInfo, IntelGeneration};
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use super::regs_gt::*;
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use crate::driver::Result;
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/// A single hardware workaround entry: register read-modify-write operation.
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@@ -221,18 +222,18 @@ pub fn build_gt_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList {
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fn gen4_gt_workarounds_init(wal: &mut WorkaroundList) {
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/* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
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wa_masked_dis(wal, 0x0210, 1 << 12, "WaDisable_RenderCache_OperationalFlush");
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wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE, "WaDisable_RenderCache_OperationalFlush");
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}
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fn g4x_gt_workarounds_init(wal: &mut WorkaroundList) {
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gen4_gt_workarounds_init(wal);
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/* WaDisableRenderCachePipelinedFlush:g4x,ilk */
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wa_masked_en(wal, 0x0210, 1 << 4, "WaDisableRenderCachePipelinedFlush");
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wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE, "WaDisableRenderCachePipelinedFlush");
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}
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fn ilk_gt_workarounds_init(wal: &mut WorkaroundList) {
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g4x_gt_workarounds_init(wal);
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wa_masked_en(wal, 0x20C4, 1 << 14, "Wa_3DChicken2_WM_Read_Pipelined");
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wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED, "Wa_3DChicken2_WM_Read_Pipelined");
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}
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fn snb_gt_workarounds_init(_wal: &mut WorkaroundList) {
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@@ -241,24 +242,24 @@ fn snb_gt_workarounds_init(_wal: &mut WorkaroundList) {
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fn ivb_gt_workarounds_init(wal: &mut WorkaroundList) {
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/* WaDisableRHWOOptimizationForRenderHang:ivb */
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wa_masked_dis(wal, 0x7018, 1 << 24, "WaDisableRHWOOptimizationForRenderHang");
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wa_masked_dis(wal, GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC, "WaDisableRHWOOptimizationForRenderHang");
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/* WaApplyL3ControlAndL3ChickenMode:ivb */
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wa_write(wal, 0xB01C, 0x7C000001, "WaApplyL3ControlAndL3ChickenMode_L3CNTL");
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wa_write(wal, 0xB024, 0x00FF0000, "WaApplyL3ControlAndL3ChickenMode_L3Chicken");
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wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL, "WaApplyL3ControlAndL3ChickenMode_L3CNTL");
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wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE, "WaApplyL3ControlAndL3ChickenMode_L3Chicken");
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/* WaForceL3Serialization:ivb */
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wa_write_clr(wal, 0xB034, 1 << 5, "WaForceL3Serialization");
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wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE, "WaForceL3Serialization");
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}
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fn hsw_gt_workarounds_init(wal: &mut WorkaroundList) {
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/* L3 caching of data atomics doesn't work -- disable it. */
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wa_write(wal, 0xB038, 1 << 16, "HSW_Scratch1_L3DataAtomicsDisable");
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wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, "HSW_Scratch1_L3DataAtomicsDisable");
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wa_add(wal, 0xE4F0, 0, (1 << 31) | (1 << 31), 0, "HSW_ROW_CHICKEN3_L3GlobalAtomicsDisable");
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wa_add(wal, HSW_ROW_CHICKEN3, 0, REG_MASKED_FIELD_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 0, "HSW_ROW_CHICKEN3_L3GlobalAtomicsDisable");
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/* WaVSRefCountFullforceMissDisable:hsw */
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wa_write_clr(wal, 0x20A0, 1 << 5, "WaVSRefCountFullforceMissDisable");
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wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME, "WaVSRefCountFullforceMissDisable");
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}
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fn gen8_gt_workarounds_init(wal: &mut WorkaroundList) {
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@@ -272,29 +273,29 @@ fn gen9_gt_workarounds_init(wal: &mut WorkaroundList, stepping: u8) {
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// the GT-level ones are relatively few.
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/* WaDisablePartialResolveInValue:gen9 */
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wa_masked_en(wal, 0xE4F0, 1 << 4, "WaDisablePartialResolveInValue");
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wa_masked_en(wal, GEN8_ROW_CHICKEN, GEN9_PARTIAL_RESOLVE_DISABLE, "WaDisablePartialResolveInValue");
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/* WaDisableRenderCachePipelinedFlush:gen9 */
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wa_masked_en(wal, 0xE180, 1 << 14, "WaDisableRenderCachePipelinedFlush");
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wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, GEN8_HSH_CHICKEN3_DOP_GATING_DISABLE, "WaDisableRenderCachePipelinedFlush");
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/* WaVFForcedNonCompressedBit:gen9 */
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wa_masked_en(wal, 0x7000, 1 << 3, "WaVFForcedNonCompressedBit");
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wa_masked_en(wal, CACHE_MODE_0_GEN7, CM0_Z_READ_OPTIMIZATION_DISABLE, "WaVFForcedNonCompressedBit");
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/* WaEnableChickenDCPR:gen9 */
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wa_masked_en(wal, 0x7004, 1 << 16, "WaEnableChickenDCPR");
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wa_masked_en(wal, CACHE_MODE_1, CM0_DEPTH_EVICT_DISABLE, "WaEnableChickenDCPR");
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/* WaAllowUMDToModifySamplerMode:gen9 */
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wa_write(wal, 0xB11C, (1 << 2) | (1 << 31), "WaAllowUMDToModifySamplerMode");
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wa_write(wal, GEN8_SAMPLER_MODE, GEN9_SAMPLER_MODE_INDIRECT_STATE_BASE_ADDR_OVERRIDE, "WaAllowUMDToModifySamplerMode");
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/* WaSetL3FreeList:gen9 */
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wa_write(wal, 0x00A0, 0x0080_0080 | (1 << 0), "WaSetL3FreeList");
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/* WaDisableRowChicken:gen9 */
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wa_masked_en(wal, 0xE4F0, 1 << 11, "WaDisableRowChicken");
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wa_masked_en(wal, GEN8_ROW_CHICKEN, GEN9_ENABLE_ROW_CHICKEN, "WaDisableRowChicken");
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if stepping == 0 {
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/* Wa_22010751155:gen9_a0 */
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wa_write_or(wal, 0x7300, 1 << 8, "Wa_22010751155");
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wa_write_or(wal, GEN9_SLICE_COMMON_ECO_CHICKEN1, 1 << 8, "Wa_22010751155");
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}
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}
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@@ -303,10 +304,10 @@ fn icl_gt_workarounds_init(wal: &mut WorkaroundList) {
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gen9_gt_workarounds_init(wal, 0);
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/* WaForwardProgressSoftReset:icl */
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wa_write_or(wal, 0xD50, 1 << 2, "WaForwardProgressSoftReset");
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wa_write_or(wal, GEN11_GT_SCRATCH, GEN11_WA_FORWARD_PROGRESS_SOFT_RESET, "WaForwardProgressSoftReset");
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/* Wa_1806527549:icl */
|
||||
wa_write_clr(wal, 0xA18C, 1 << 2, "Wa_1806527549");
|
||||
wa_write_clr(wal, GEN11_GT_SCRATCH, GEN11_WA_1806527549, "Wa_1806527549");
|
||||
}
|
||||
|
||||
fn gen12_gt_workarounds_init(wal: &mut WorkaroundList, stepping: u8) {
|
||||
@@ -314,26 +315,26 @@ fn gen12_gt_workarounds_init(wal: &mut WorkaroundList, stepping: u8) {
|
||||
gen9_gt_workarounds_init(wal, stepping);
|
||||
|
||||
/* Wa_14017192718:gen12 */
|
||||
wa_write_or(wal, 0xA18C, 1 << 8, "Wa_14017192718");
|
||||
wa_write_or(wal, GEN11_GT_SCRATCH, 1 << 8, "Wa_14017192718");
|
||||
|
||||
/* Wa_14012688713:gen12 */
|
||||
wa_write_or(wal, 0xA18C, 1 << 9, "Wa_14012688713");
|
||||
wa_write_or(wal, GEN11_GT_SCRATCH, 1 << 9, "Wa_14012688713");
|
||||
|
||||
/* Wa_16013039831:gen12 */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 11, "Wa_16013039831");
|
||||
wa_masked_en(wal, GEN8_ROW_CHICKEN, GEN9_ENABLE_ROW_CHICKEN, "Wa_16013039831");
|
||||
|
||||
/* Wa_14013676891:gen12 */
|
||||
wa_write_or(wal, 0xB11C, 1 << 8, "Wa_14013676891");
|
||||
wa_write_or(wal, GEN8_SAMPLER_MODE, 1 << 8, "Wa_14013676891");
|
||||
|
||||
/* Wa_16012751909:gen12 */
|
||||
wa_write_or(wal, 0x55B0, (1 << 9) | (1 << 12), "Wa_16012751909");
|
||||
wa_write_or(wal, GEN12_COMMON_SLICE_CHICKEN2, GEN12_CSC2_SCOREBOARD_STALL_FLUSH_CONTROL, "Wa_16012751909");
|
||||
|
||||
/* Wa_16012322899:gen12 */
|
||||
wa_write_or(wal, 0xE180, 1 << 14, "Wa_16012322899");
|
||||
wa_write_or(wal, GEN7_HALF_SLICE_CHICKEN1, GEN8_HSH_CHICKEN3_DOP_GATING_DISABLE, "Wa_16012322899");
|
||||
|
||||
if stepping == 0 {
|
||||
/* Wa_16012650089:gen12_a0 */
|
||||
wa_write_or(wal, 0x7300, 1 << 8, "Wa_16012650089");
|
||||
wa_write_or(wal, GEN9_SLICE_COMMON_ECO_CHICKEN1, 1 << 8, "Wa_16012650089");
|
||||
}
|
||||
}
|
||||
|
||||
@@ -350,10 +351,8 @@ pub fn build_ctx_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList {
|
||||
match gen {
|
||||
IntelGeneration::Gen6 => gen6_ctx_workarounds_init(&mut wal),
|
||||
IntelGeneration::Gen7 => gen7_ctx_workarounds_init(&mut wal),
|
||||
IntelGeneration::Gen7 => gen7_ctx_workarounds_init(&mut wal),
|
||||
IntelGeneration::Gen8 => gen8_ctx_workarounds_init(&mut wal),
|
||||
IntelGeneration::Gen9 => gen9_ctx_workarounds_init(&mut wal),
|
||||
IntelGeneration::Gen9_5 => gen9_ctx_workarounds_init(&mut wal),
|
||||
IntelGeneration::Gen9_5 => icl_ctx_workarounds_init(&mut wal),
|
||||
IntelGeneration::Gen12 => gen12_ctx_workarounds_init(&mut wal),
|
||||
_ => {}
|
||||
|
||||
Reference in New Issue
Block a user