Files
RedBear-OS/local/recipes/dev
vasilito d5636ae1de intel: P0/P1 — LRC context state, MI commands, DDI sequences, pipe scaler
context.rs: proper LRC image population
  Removed context restore inhibit — GPU now saves/restores state on preempt
  Added PDP register initialization in LRC image (4 PDP entries)
  Added FAULT_AND_STREAM_CTL, BB_STATE initialization
  set_pdp_registers() for per-context PPGTT configuration

ring.rs: MI command emission helpers
  emit_bb_start/emit_bb_end: batch buffer chaining
  emit_load_register_imm: LRI for workaround application
  emit_store_data_imm: store-to-memory for fence signaling
  emit_arb_check: preemption point insertion
  emit_semaphore_wait: inter-engine synchronization
  emit_user_interrupt: explicit interrupt generation

display.rs: DDI pre-enable/post-disable sequences
  ddi_pre_enable: DP link retrain + DDI_BUF_CTL enable with pipe routing
  ddi_post_disable: DDI_BUF_CTL, PIPECONF, DSPCNTR disable + pipe update
  Pipe scaler PS_CTRL/PS_WIN_POS/PS_WIN_SIZE programming in set_mode

regs.rs + regs_gen9/gen12/xe2: scaler register trait methods
  ps_ctrl, ps_win_pos, ps_win_size at 0x68180/0x68170/0x68174 per pipe
2026-06-01 23:58:13 +03:00
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