240e59e2bf
Handle pci buses without a device at the first slot
2024-01-19 14:45:48 +01:00
c611988768
Fix MCFG parsing for PCIe
2024-01-19 13:19:53 +01:00
b317484d67
Simplify Mcfgs::fetch
2024-01-19 13:00:23 +01:00
15249127a5
Fix a couple of warnings
2024-01-19 12:47:42 +01:00
d010d03eef
Fix pcid tests
2024-01-19 12:40:55 +01:00
2b5ed69a06
Use PciAddress in a couple more places
2024-01-19 12:40:54 +01:00
42b2f52d41
Directly store a PciAddress inside PciFunc instead of a PciDev + num
2024-01-19 12:29:22 +01:00
e5491a9e9a
Inline several layers of read and write methods
2024-01-19 12:21:22 +01:00
336903b90a
Introduce SharedPciHeader to deduplicate fields between the General and PciToPci variants
2024-01-19 12:14:02 +01:00
a7c5391c6c
Introduce PciAddress type copied from the pci_types crate
2024-01-19 12:14:00 +01:00
07d5d730d2
Remove nolock CfgAccess methods
...
They are only called by the corresponding locked methods.
2024-01-18 22:14:04 +01:00
61e9512468
Update redox_syscall to 0.4
2023-09-07 20:49:37 -06:00
ba661f9719
Replace SYS_PIPE2 with libc::pipe in pcid.
2023-08-31 21:20:23 +02:00
156be64a9d
pcid: replace add that should allow wrapping with explicit wrapping_add
2023-07-27 01:22:56 -07:00
e0a0e2a532
Remove physmap in pcid.
2023-07-18 11:01:16 +02:00
7e5a3196c2
pcid::server_handle: add get_capabilities
...
This commit adds the `get_capabilities` function to `PcidServerHandle`
which returns all of the `Capability`s (raw representation) of the PCI
device.
Signed-off-by: Anhad Singh <andypython@protonmail.com >
2023-06-19 12:18:56 +10:00
a5a3f3341f
Remove all usages of physunmap.
2023-06-11 11:33:27 +02:00
96246acca5
pcid: Optimize PCI bus scanning
2023-02-15 20:05:25 -07:00
5bbe2e3f4c
ahci, ihda, pci, xhci: logging adjustments
2023-02-15 19:30:59 -07:00
625064004d
Update for new Rust nightly
2023-02-11 14:37:22 -07:00
a6bafa17b0
Add pcid methods to read/write pci config region
2022-09-12 21:47:16 -06:00
e2a8255547
Allow reading PCI header through pcid socket
2022-09-07 12:15:41 -06:00
4bca3e55d3
Fix xhcid compilation
2022-08-31 08:49:39 -06:00
0e85c01ea3
Implement 64-bit BARs
2022-08-31 08:46:53 -06:00
af873f7626
Update redox_syscall dependency.
2022-07-27 17:55:39 +02:00
21e30b7339
Replace syscall::clone() with libc::fork().
2022-07-27 16:25:01 +02:00
da8ecef8a7
Workarounds for aarch64 support
2022-07-26 16:11:45 -06:00
07f10fb4d1
Update redox_syscall to v0.2.12
2022-03-24 16:06:00 +01:00
d426ffacea
Update toolchain to 2022-03-18.
2022-03-19 15:06:29 +01:00
5e42b0697e
Skip parsing vendor caps with length 0
2022-02-11 09:23:48 -07:00
7a2b3d7656
Update dependencies.
2021-06-17 18:18:27 +02:00
00b7674321
Use correct syscall when dropping PCIe context.
2021-03-08 14:37:38 +01:00
31bae74334
Merge branch 'code_hygiene' into 'master'
...
Code hygiene
See merge request redox-os/drivers!72
2020-08-08 12:55:24 +00:00
be101621cc
Update to newer syscall
2020-08-02 15:25:03 -06:00
6018b6fc49
Fix lint issues from rustc.
...
Signed-off-by: Wren Turkal <wt@penguintechs.org >
2020-08-01 16:52:47 -07:00
dadc0c6c10
Remove unused imports.
...
Signed-off-by: Wren Turkal <wt@penguintechs.org >
2020-08-01 12:48:06 -07:00
63dc11fbb9
Merge branch 'add_pci_vendor_specific_capability' into 'master'
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Add pci vendor specific capability.
See merge request redox-os/drivers!71
2020-08-01 18:18:31 +00:00
7b8485a582
Merge branch 'pci_ids_info' into 'master'
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Add more structure cli to pcid.
See merge request redox-os/drivers!67
2020-08-01 18:16:31 +00:00
65982d5e02
Add more structure cli to pcid.
...
This change adds a structopt commandline interface to the pcid tool.
This add some help for the arguments that pcid takes.
Signed-off-by: Wren Turkal <wt@penguintechs.org >
2020-08-01 18:16:31 +00:00
39fea64403
Add pci vendor specific capability.
...
Signed-off-by: Wren Turkal <wt@penguintechs.org >
2020-08-01 00:40:30 -07:00
5db50db7a9
Fix buggy assertion in pcid capability parser.
...
The pcid capability parsing code has an assertion that checks for dword
alignment. Unfortunately, the check was previously checking for
alignment to qwords. This fixes that.
I found this issue by using qemu to emulate adding different pci
devices. I managed to come across a device that had a capability
aligned on dword, but not qword. That exposed the bug.
Signed-off-by: Wren Turkal <wt@penguintechs.org >
2020-07-31 21:39:21 -07:00
5dfd5f7e7c
Fixed PCI bus scan to scan bus 0xFF.
...
Previously, the PCI bus scan was skipping bus 0xFF. Now it does not.
I used a match expression to make sure that all cases are accounted for.
I also changed the PCI dev scan and PCI func scan to use a match
expression in a similar way to make sure all cases are account. While
this is functionally the same as before, the match expression will not
allow unhandled cases and should be easier to read and make it harder
to introduce bugs.
Signed-off-by: Wren Turkal <wt@penguintechs.org >
2020-07-27 22:49:39 -07:00
24aa9192cb
pcid: Fix extra newlines in log
2020-07-15 22:23:34 -06:00
146265682a
Improved PCI capability parsing.
2020-05-21 12:16:22 +00:00
cea6ce7d7a
Move the setrens to a later position, in nvmed.
2020-05-02 00:05:04 +02:00
c61e886108
Refactor and rustfmt the nvme driver.
2020-05-01 11:57:55 +02:00
d485176bd6
Improve startup interrupt initialization.
2020-04-27 15:59:06 +02:00
4016b0c7b8
Fix failing pcid config parsing.
2020-04-23 15:35:44 +02:00
7b69d5b9b5
WIP: Use the enhanced pcid IPC.
2020-04-22 21:21:55 +02:00
07d4ae0e60
Recognize the AHCI-specific SATA PCI capability.
2020-04-22 18:52:51 +02:00
bjorn3