Workarounds for aarch64 support

acpid/src/aml/mod.rs

@@ -4,6 +4,7 @@
 
 use std::collections::HashMap;
 
+#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 use syscall::io::{Io, Pio};
 
 use crate::acpi::{AcpiContext, AmlContainingTable, Sdt, SdtHeader};
@@ -126,8 +127,16 @@ pub fn set_global_s_state(context: &AcpiContext, state: u8) {
     log::info!("Shutdown SLP_TYPa {:X}, SLP_TYPb {:X}", slp_typa, slp_typb);
     val |= slp_typa as u16;
 
-    log::info!("Shutdown with ACPI outw(0x{:X}, 0x{:X})", port, val);
-    Pio::<u16>::new(port).write(val);
+    #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+    {
+        log::info!("Shutdown with ACPI outw(0x{:X}, 0x{:X})", port, val);
+        Pio::<u16>::new(port).write(val);
+    }
+
+    #[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
+    {
+        log::error!("Cannot shutdown with ACPI outw(0x{:X}, 0x{:X}) on this architecture", port, val);
+    }
 
     loop {
         core::hint::spin_loop();

nvmed/src/main.rs

@@ -1,3 +1,5 @@
+#![cfg_attr(target_arch = "aarch64", feature(stdsimd))] // Required for yield instruction
+
 use std::convert::TryInto;
 use std::fs::File;
 use std::io::{ErrorKind, Read, Write};

nvmed/src/nvme/mod.rs

@@ -24,7 +24,7 @@ use pcid_interface::PcidServerHandle;
 
 #[cfg(target_arch = "aarch64")]
 #[inline(always)]
-pub(crate) unsafe fn pause() { std::arch::x86::__yield(); }
+pub(crate) unsafe fn pause() { std::arch::aarch64::__yield(); }
 
 #[cfg(target_arch = "x86")]
 #[inline(always)]

pcid/src/pci/mod.rs

@@ -1,6 +1,7 @@
 use std::convert::TryFrom;
 use std::sync::{Mutex, Once};
 
+#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 use syscall::io::{Io as _, Pio};
 
 pub use self::bar::PciBar;
@@ -96,6 +97,25 @@ impl CfgAccess for Pci {
         self.write_nolock(bus, dev, func, offset, value)
     }
 }
+#[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
+impl CfgAccess for Pci {
+    unsafe fn read_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
+        todo!("Pci::CfgAccess::read_nolock on this architecture")
+    }
+
+    unsafe fn read(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
+        let _guard = self.lock.lock().unwrap();
+        self.read_nolock(bus, dev, func, offset)
+    }
+
+    unsafe fn write_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
+        todo!("Pci::CfgAccess::write_nolock on this architecture")
+    }
+    unsafe fn write(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
+        let _guard = self.lock.lock().unwrap();
+        self.write_nolock(bus, dev, func, offset, value)
+    }
+}
 
 pub struct PciIter<'pci> {
     pci: &'pci dyn CfgAccess,