Add write combining page flags where applicable

src/arch/aarch64.rs

@@ -32,6 +32,7 @@ impl Arch for AArch64Arch {
     const ENTRY_FLAG_EXEC: usize = 0;
     const ENTRY_FLAG_GLOBAL: usize = 0;
     const ENTRY_FLAG_NO_GLOBAL: usize = 1 << 11;
+    const ENTRY_FLAG_WRITE_COMBINING: usize = 0;
 
     const PHYS_OFFSET: usize = 0xFFFF_8000_0000_0000;
 

src/arch/emulate.rs

@@ -31,6 +31,8 @@ impl Arch for EmulateArch {
 
     const ENTRY_ADDRESS_WIDTH: usize = X8664Arch::ENTRY_ADDRESS_WIDTH;
 
+    const ENTRY_FLAG_WRITE_COMBINING: usize = X8664Arch::ENTRY_FLAG_WRITE_COMBINING;
+
     unsafe fn init() -> &'static [MemoryArea] {
         // Create machine with PAGE_ENTRIES pages offset mapped (2 MiB on x86_64)
         let mut machine = Machine::new(MEMORY_SIZE);

src/arch/mod.rs

@@ -43,6 +43,7 @@ pub trait Arch: Clone + Copy {
     const ENTRY_FLAG_EXEC: usize;
     const ENTRY_FLAG_GLOBAL: usize;
     const ENTRY_FLAG_NO_GLOBAL: usize;
+    const ENTRY_FLAG_WRITE_COMBINING: usize;
 
     const PHYS_OFFSET: usize;
 

src/arch/riscv64/sv39.rs

@@ -24,6 +24,7 @@ impl Arch for RiscV64Sv39Arch {
     const ENTRY_FLAG_EXEC: usize = 1 << 3;
     const ENTRY_FLAG_GLOBAL: usize = 1 << 5;
     const ENTRY_FLAG_NO_GLOBAL: usize = 0;
+    const ENTRY_FLAG_WRITE_COMBINING: usize = 0;
 
     const PHYS_OFFSET: usize = 0xFFFF_FFC0_0000_0000;
 

src/arch/riscv64/sv48.rs

@@ -24,6 +24,7 @@ impl Arch for RiscV64Sv48Arch {
     const ENTRY_FLAG_EXEC: usize = 1 << 3;
     const ENTRY_FLAG_GLOBAL: usize = 1 << 5;
     const ENTRY_FLAG_NO_GLOBAL: usize = 0;
+    const ENTRY_FLAG_WRITE_COMBINING: usize = 0;
 
     const PHYS_OFFSET: usize = 0xFFFF_8000_0000_0000;
 

src/arch/x86.rs

@@ -23,6 +23,7 @@ impl Arch for X86Arch {
     const ENTRY_FLAG_NO_GLOBAL: usize = 0;
     const ENTRY_FLAG_NO_EXEC: usize = 0; // NOT AVAILABLE UNLESS PAE IS USED!
     const ENTRY_FLAG_EXEC: usize = 0;
+    const ENTRY_FLAG_WRITE_COMBINING: usize = 1 << 7;
 
     const PHYS_OFFSET: usize = 0x8000_0000;
 

src/arch/x86_64.rs

@@ -22,6 +22,7 @@ impl Arch for X8664Arch {
     const ENTRY_FLAG_NO_GLOBAL: usize = 0;
     const ENTRY_FLAG_NO_EXEC: usize = 1 << 63;
     const ENTRY_FLAG_EXEC: usize = 0;
+    const ENTRY_FLAG_WRITE_COMBINING: usize = 1 << 7;
 
     const PHYS_OFFSET: usize = Self::PAGE_NEGATIVE_MASK + (Self::PAGE_ADDRESS_SIZE >> 1) as usize; // PML4 slot 256 and onwards
 

src/page/flags.rs

@@ -56,6 +56,12 @@ impl<A: Arch> PageFlags<A> {
         self
     }
 
+    #[must_use]
+    #[inline(always)]
+    pub fn write_combining(self, value: bool) -> Self {
+        self.custom_flag(A::ENTRY_FLAG_WRITE_COMBINING, value)
+    }
+
     #[inline(always)]
     pub fn has_flag(&self, flag: usize) -> bool {
         self.data & flag == flag