RISC-V: implement TLB flush

src/arch/riscv64/sv39.rs

@@ -32,9 +32,13 @@ impl Arch for RiscV64Sv39Arch {
     }
 
     #[inline(always)]
-    unsafe fn invalidate(_address: VirtualAddress) {
-        //TODO: can one address be invalidated?
-        Self::invalidate_all();
+    unsafe fn invalidate(address: VirtualAddress) {
+        asm!("sfence.vma {}", in(reg) address.data());
+    }
+
+    #[inline(always)]
+    unsafe fn invalidate_all() {
+        asm!("sfence.vma");
     }
 
     #[inline(always)]
@@ -51,6 +55,7 @@ impl Arch for RiscV64Sv39Arch {
         let satp = (8 << 60) | // Sv39 MODE
             (address.data() >> Self::PAGE_SHIFT); // Convert to PPN (TODO: ensure alignment)
         asm!("csrw satp, {0}", in(reg) satp);
+        Self::invalidate_all();
     }
 
     fn virt_is_valid(address: VirtualAddress) -> bool {

src/arch/riscv64/sv48.rs

@@ -32,9 +32,13 @@ impl Arch for RiscV64Sv48Arch {
     }
 
     #[inline(always)]
-    unsafe fn invalidate(_address: VirtualAddress) {
-        //TODO: can one address be invalidated?
-        Self::invalidate_all();
+    unsafe fn invalidate(address: VirtualAddress) {
+        asm!("sfence.vma {}", in(reg) address.data());
+    }
+
+    #[inline(always)]
+    unsafe fn invalidate_all() {
+        asm!("sfence.vma");
     }
 
     #[inline(always)]
@@ -51,7 +55,9 @@ impl Arch for RiscV64Sv48Arch {
         let satp = (9 << 60) | // Sv48 MODE
             (address.data() >> Self::PAGE_SHIFT); // Convert to PPN (TODO: ensure alignment)
         asm!("csrw satp, {0}", in(reg) satp);
+        Self::invalidate_all();
     }
+
     fn virt_is_valid(address: VirtualAddress) -> bool {
         // RISC-V SV48 uses 48-bit sign-extended addresses, identical to 4-level paging on x86_64.
         let mask = !((Self::PAGE_ADDRESS_SIZE as usize - 1) >> 1);