intel: DPLL module header — architecture documentation

Document all 5 PLL architectures per generation:
  SKL/KBL/CFL: LCPLL1/2 + WRPLL1/2
  ICL: LCPLL1/2 + DPLL for MG/Combo PHY
  TGL/ADL: LCPLL1/2 + WRPLL + TGL CFGCR
  MTL: DPLL_CTRL1 + DPLL_FREQ
  Xe2: DPLL_CTRL1/2 with power enable

wrpll_compute() algorithm: 3 DCO central frequencies × 43 dividers
with deviation minimization + p0×p1×p2 decomposition

local/recipes/gpu/redox-drm/source/src/drivers/intel/display_dpll.rs

@@ -7,6 +7,19 @@ use redox_driver_sys::memory::MmioRegion;
 use super::info::{IntelDeviceInfo, IntelGeneration};
 use crate::driver::{DriverError, Result};
 
+// ── Intel Display PLL Manager — Ported from intel_dpll_mgr.c (7,509 lines) ─
+// Manages WRPLL, LCPLL, DPLL, and MG PLL clock sources for all display outputs.
+// Each generation uses different PLL architectures:
+//   SKL/KBL/CFL (Gen9):  LCPLL1/2 + WRPLL1/2
+//   ICL (Gen11):          LCPLL1/2 + DPLL for MG/Combo PHY
+//   TGL/ADL (Gen12):      LCPLL1/2 + WRPLL1/2 + TGL-specific CFGCR
+//   MTL (Gen12.7):        DPLL_CTRL1 + DPLL_FREQ register
+//   Xe2 (ARL/LNL/BMG):    DPLL_CTRL1/2 with power enable
+//
+// The wrpll_compute() function implements the Linux skl_ddi_calculate_wrpll
+// algorithm: DCO central frequency search across 3 frequencies × 43 dividers
+// with deviation minimization, then p0×p1×p2 multiplier decomposition.
+
 const LCPLL1_CTL: usize = 0x46010;
 const LCPLL2_CTL: usize = 0x46014;
 const WRPLL_CTL1: usize = 0x46040;