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fix: correct P20 patch line numbers from actual diff

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- Derived line offsets from real pre-P20 vs post-P20 diff
- x86.rs: 3 hunks at @@ -446/-456/-468 converting hardcoded <<32 to
  local_apic.x2-gated format with xAPIC <<56 fallback
- local_apic.rs: 1 hunk promoting debug! to info! for bootlog visibility
This commit is contained in:
Admin Pupkin
2026-05-17 14:51:58 +03:00
parent 6f12b4e2a8
commit ea7234f44b
1 changed files with 8 additions and 16 deletions
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local/patches/kernel/P20-x2apic-icr-mode-fix.patch
+8 -16
View File
@@ -1,7 +1,7 @@
diff --git a/src/acpi/madt/arch/x86.rs b/src/acpi/madt/arch/x86.rs
--- a/src/acpi/madt/arch/x86.rs
+++ b/src/acpi/madt/arch/x86.rs
@@ -444,28 +444,40 @@
@@ -446,7 +446,11 @@
// Send INIT IPI (Assert)
{
let mut icr = 0x4500u64;
@@ -13,13 +13,8 @@ diff --git a/src/acpi/madt/arch/x86.rs b/src/acpi/madt/arch/x86.rs
+ }
local_apic.set_icr(icr);
}
-
+
// Intel SDM Vol 3A §8.4.4: wait 10ms after INIT
early_udelay(10_000);
-
+
// Send START IPI #1
@@ -456,7 +460,11 @@
{
let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
let mut icr = 0x0600u64 | ap_segment as u64;
@@ -31,13 +26,8 @@ diff --git a/src/acpi/madt/arch/x86.rs b/src/acpi/madt/arch/x86.rs
+ }
local_apic.set_icr(icr);
}
-
+
// Intel SDM: wait 200µs between SIPIs
early_udelay(200);
-
+
// Send START IPI #2 (recommended for compatibility)
@@ -468,7 +476,11 @@
{
let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
let mut icr = 0x0600u64 | ap_segment as u64;
@@ -49,10 +39,11 @@ diff --git a/src/acpi/madt/arch/x86.rs b/src/acpi/madt/arch/x86.rs
+ }
local_apic.set_icr(icr);
}
diff --git a/src/arch/x86_shared/device/local_apic.rs b/src/arch/x86_shared/device/local_apic.rs
--- a/src/arch/x86_shared/device/local_apic.rs
+++ b/src/arch/x86_shared/device/local_apic.rs
@@ -60,7 +60,7 @@
@@ -61,9 +61,9 @@
if !self.x2 {
- debug!("Detected xAPIC at {:#x}", physaddr.data());
@@ -62,3 +53,4 @@ diff --git a/src/arch/x86_shared/device/local_apic.rs b/src/arch/x86_shared/devi
- debug!("Detected x2APIC");
+ info!("Detected x2APIC");
}