intel: add DP protocol comments to dp_aux.rs constants
Document DisplayPort 1.4 specification constants: AUX channel register layout (0x64010 base, 0x100 stride) AUX transaction timeout rationale (300us spec + PM margin) DPCD capability register addresses (revision, link rate, lane count) I2C-over-AUX EDID addressing (0x50 EEPROM, segment pointers) AUX transaction types (native READ/WRITE, I2C READ/WRITE, MOT flag)
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@@ -17,27 +17,33 @@ const DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT: u32 = 20;
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const DP_AUX_CH_CTL_MESSAGE_SIZE_MASK: u32 = 0x1F;
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const DP_AUX_CH_CTL_SEND: u32 = 1 << 0;
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// DP AUX channel register base. Each port has its own set at AUX_STRIDE intervals.
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const DP_AUX_CTL_BASE: usize = 0x64010;
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const DP_AUX_DATA_BASE: usize = 0x64014;
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const AUX_STRIDE: usize = 0x100;
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// AUX transaction timeout in milliseconds. The DP spec allows up to 300us for
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// AUX native transactions, but sink devices may take longer under power management.
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const AUX_TIMEOUT_MS: u64 = 10;
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const AUX_DEFER_MAX_RETRIES: u32 = 7;
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// DPCD register addresses for capability discovery and sink communication.
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const DPCD_REV: u32 = 0x0000;
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const DPCD_MAX_LINK_RATE: u16 = 0x0001;
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const DPCD_MAX_LANE_COUNT: u16 = 0x0002;
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// I2C-over-AUX addresses for EDID. The EDID EEPROM is always at I2C address 0x50.
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const EDID_I2C_ADDRESS: u8 = 0x50;
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const EDID_SEGMENT_ADDR: u8 = 0x30;
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const EDID_DDC_SEGMENT_ADDR: u8 = 0x60;
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const EDID_LENGTH: usize = 128;
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// AUX transaction types as defined by the DP 1.4 specification.
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const AUX_NATIVE_WRITE: u8 = 0x00;
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const AUX_NATIVE_READ: u8 = 0x01;
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const AUX_I2C_WRITE: u8 = 0x04;
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const AUX_I2C_READ: u8 = 0x05;
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const AUX_I2C_MOT: u8 = 0x02;
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const AUX_I2C_MOT: u8 = 0x02; // Middle-of-Transaction flag for multi-byte I2C
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pub struct DpAux {
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mmio: Arc<MmioRegion>,
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