Merge branch 'pci_types_update_interrupt' into 'master'

Use pci_types for setting the interrupt line

See merge request redox-os/drivers!157

Cargo.lock

@@ -907,9 +907,9 @@ checksum = "7f0b59668fe80c5afe998f0c0bf93322bf2cd66cafeeb80581f291716f3467f2"
 
 [[package]]
 name = "pci_types"
-version = "0.9.0"
+version = "0.9.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6f966dfb3dde50a726cc62ae44dc48efd10a211db15296c00cd88550ad8ef24c"
+checksum = "d6848549f754bd20aa382ffec0f4f04ba50e55a18ff75a0862bf9e227fe42b57"
 dependencies = [
  "bit_field",
  "bitflags 2.5.0",

pcid/Cargo.toml

@@ -20,7 +20,7 @@ fdt = { git = "https://gitlab.redox-os.org/rosehuds/fdt.git" }
 libc = "0.2"
 log = "0.4"
 paw = "1.0"
-pci_types = "0.9.0"
+pci_types = "0.9.1"
 plain = "0.2"
 redox-log = "0.1"
 redox_syscall = "0.5"

pcid/src/main.rs

@@ -256,7 +256,7 @@ fn handle_parsed_header(state: Arc<State>, config: &Config, header: PciEndpointH
             info!("    BAR{}", string);
         }
 
-        let endpoint_header = header.endpoint_header(&state.pcie);
+        let mut endpoint_header = header.endpoint_header(&state.pcie);
 
         // Enable bus mastering, memory space, and I/O space
         endpoint_header.update_command(&state.pcie, |cmd| {
@@ -266,20 +266,17 @@ fn handle_parsed_header(state: Arc<State>, config: &Config, header: PciEndpointH
         });
 
         // Set IRQ line to 9 if not set
-        let mut irq;
-        let interrupt_pin;
+        let mut irq = 0xFF;
+        let mut interrupt_pin = 0xFF;
 
-        // FIXME use pci_types' update_interrupt once it is released to crates.io
-        unsafe {
-            let mut data = state.pcie.read(header.address(), 0x3C);
-            irq = (data & 0xFF) as u8;
-            interrupt_pin = ((data & 0x0000_FF00) >> 8) as u8;
-            if irq == 0xFF {
-                irq = 9;
+        endpoint_header.update_interrupt(&state.pcie, |(pin, mut line)| {
+            if line == 0xFF {
+                line = 9;
             }
-            data = (data & 0xFFFFFF00) | irq as u32;
-            state.pcie.write(header.address(), 0x3C, data);
-        };
+            irq = line;
+            interrupt_pin = pin;
+            (pin, line)
+        });
 
         let legacy_interrupt_enabled = match interrupt_pin {
             0 => false,