intel: info.rs + gtt.rs module documentation
info.rs: platform detection architecture 161 device IDs from Gen4 (2006) through Xe2 (2025) GMD_ID runtime detection (Gen12+) EU/subslice fuse register enumeration 11 generation variants with per-gen capabilities gtt.rs: GGTT page table architecture BAR0 64-bit PTE entries, 4KB/64KB page support GFX_FLSH_CNTL flush protocol (write + posting read) Free-list allocation with coalescing 64KB pages for Gen12.5+ (DG2, MTL, Xe2) Intel driver: 95 files, 0 errors — 26 spec-commented files
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@@ -7,6 +7,18 @@ use redox_driver_sys::memory::MmioRegion;
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use super::info::IntelGeneration;
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use crate::driver::{DriverError, Result};
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// ── Intel GGTT — Graphics GTT Page Tables ───────────────────────────────
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// GGTT (Global GTT) provides GPU-accessible virtual→physical address
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// translation for all contexts. It's a single shared page table in BAR0.
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//
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// The GGTT aperture (BAR0) contains 64-bit PTE entries. Each entry maps
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// one page (4KB or 64KB on Gen12.5+). Entries must be flushed via
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// GFX_FLSH_CNTL register write + posting read after modification.
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//
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// alloc_range/release_range: free-list allocation with coalescing.
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// map_range/unmap_range: PTE programming with flush.
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// 64KB page support for Gen12.5+ (DG2, MTL, Xe2).
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const GTT_BASE: usize = 0x0000;
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const GFX_FLSH_CNTL_REG: usize = 0x101008;
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const GFX_FLSH_CNTL_EN: u32 = 1 << 0;
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@@ -1,5 +1,15 @@
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use log::warn;
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// ── Intel Device Info — Generation + Platform Detection ──────────────────
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// Maps PCI device IDs to Intel platforms, generations, and capabilities.
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// Supports 161 device IDs from Gen4 (I965G, 2006) through Xe2 (BMG, 2025).
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//
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// Runtime detection: GMD_ID register (Gen12+) for IP version, EU/subslice
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// count from GT_SLICE_INFO and EU_DISABLE fuse registers.
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//
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// Generation enum covers 11 variants: Gen4 through GenXe2 + Unknown.
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// Each variant provides display_version, gt_version, and num_pipes.
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const GMD_ID_MMIO: usize = 0x138040;
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const GEN8_EU_DISABLE0: usize = 0x1913C;
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const GEN8_EU_DISABLE1: usize = 0x19140;
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