From 9b8c69d842898e3b9bda241cc6251200513dec5c Mon Sep 17 00:00:00 2001
From: Admin Pupkin <adminpupkin@gmail.com>
Date: Tue, 2 Jun 2026 11:35:56 +0300
Subject: [PATCH] intel: info.rs + gtt.rs module documentation
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info.rs: platform detection architecture
  161 device IDs from Gen4 (2006) through Xe2 (2025)
  GMD_ID runtime detection (Gen12+)
  EU/subslice fuse register enumeration
  11 generation variants with per-gen capabilities

gtt.rs: GGTT page table architecture
  BAR0 64-bit PTE entries, 4KB/64KB page support
  GFX_FLSH_CNTL flush protocol (write + posting read)
  Free-list allocation with coalescing
  64KB pages for Gen12.5+ (DG2, MTL, Xe2)

Intel driver: 95 files, 0 errors — 26 spec-commented files
---
 .../gpu/redox-drm/source/src/drivers/intel/gtt.rs    | 12 ++++++++++++
 .../gpu/redox-drm/source/src/drivers/intel/info.rs   | 10 ++++++++++
 2 files changed, 22 insertions(+)

diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/gtt.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/gtt.rs
index bf472a856a..59aff67e42 100644
--- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/gtt.rs
+++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/gtt.rs
@@ -7,6 +7,18 @@ use redox_driver_sys::memory::MmioRegion;
 use super::info::IntelGeneration;
 use crate::driver::{DriverError, Result};
 
+// ── Intel GGTT — Graphics GTT Page Tables ───────────────────────────────
+// GGTT (Global GTT) provides GPU-accessible virtual→physical address
+// translation for all contexts. It's a single shared page table in BAR0.
+//
+// The GGTT aperture (BAR0) contains 64-bit PTE entries. Each entry maps
+// one page (4KB or 64KB on Gen12.5+). Entries must be flushed via
+// GFX_FLSH_CNTL register write + posting read after modification.
+//
+// alloc_range/release_range: free-list allocation with coalescing.
+// map_range/unmap_range: PTE programming with flush.
+// 64KB page support for Gen12.5+ (DG2, MTL, Xe2).
+
 const GTT_BASE: usize = 0x0000;
 const GFX_FLSH_CNTL_REG: usize = 0x101008;
 const GFX_FLSH_CNTL_EN: u32 = 1 << 0;
diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/info.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/info.rs
index 95c4275818..ee51171743 100644
--- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/info.rs
+++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/info.rs
@@ -1,5 +1,15 @@
 use log::warn;
 
+// ── Intel Device Info — Generation + Platform Detection ──────────────────
+// Maps PCI device IDs to Intel platforms, generations, and capabilities.
+// Supports 161 device IDs from Gen4 (I965G, 2006) through Xe2 (BMG, 2025).
+//
+// Runtime detection: GMD_ID register (Gen12+) for IP version, EU/subslice
+// count from GT_SLICE_INFO and EU_DISABLE fuse registers.
+//
+// Generation enum covers 11 variants: Gen4 through GenXe2 + Unknown.
+// Each variant provides display_version, gt_version, and num_pipes.
+
 const GMD_ID_MMIO: usize = 0x138040;
 const GEN8_EU_DISABLE0: usize = 0x1913C;
 const GEN8_EU_DISABLE1: usize = 0x19140;