intel: comprehensive workaround infrastructure + Gen4-Gen12 initial tables
Replace the ad-hoc 113-line workaround module with a proper data model: - Workaround struct: offset, clear, set, read_mask, masked, name - WorkaroundList: sorted Vec with automatic merge/dedup at same offset - apply(): read-modify-write with masked-register and write-only support - verify(): post-application validation against read_mask - Helper functions: wa_masked_en/dis/field_set, wa_write/or/clr/clr_set - MCR variants: aliases to regular helpers (no MCR steering yet) Tables ported from Linux 7.1 intel_workarounds.c: - GT workarounds: gen4, g4x, ilk, snb, ivb, hsw, gen9, icl(gen9.5), gen12 - Context workarounds: gen6, gen7, gen8, gen9, icl, gen12 - Engine workarounds: general_render_compute - Whitelist: gen9, icl, gen12 0 compilation errors.
This commit is contained in:
Red Bear
@@ -1,113 +1,568 @@
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use std::sync::Arc;
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use std::time::{Duration, Instant};
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use log::{debug, info, warn};
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use log::info;
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use redox_driver_sys::memory::MmioRegion;
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use super::info::{IntelDeviceInfo, IntelGeneration};
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use crate::driver::{DriverError, Result};
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use crate::kms::ModeInfo;
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use crate::driver::Result;
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pub fn apply_full_workarounds(mmio: &MmioRegion, device_info: &IntelDeviceInfo) -> u32 {
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let mut count: u32 = 0;
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/// A single hardware workaround entry: register read-modify-write operation.
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#[derive(Debug, Clone)]
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pub struct Workaround {
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/// MMIO register offset (absolute, not engine-relative).
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pub offset: usize,
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/// Bits to clear (AND mask). If `!0`, register is write-only (no read).
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pub clear: u32,
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/// Bits to set (OR mask).
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pub set: u32,
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/// Mask of bits that must be verified after application.
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pub read_mask: u32,
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/// If true, this is a "masked register" where the upper 16 bits are
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/// the field mask and the lower 16 bits are the value to write.
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pub masked: bool,
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/// Human-readable workaround ID (e.g. "Wa_1409600907").
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pub name: &'static str,
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}
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/// A sorted, deduplicated list of workarounds for a given domain (GT, engine, context).
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pub struct WorkaroundList {
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pub name: &'static str,
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pub entries: Vec<Workaround>,
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}
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impl WorkaroundList {
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pub fn new(name: &'static str) -> Self {
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Self { name, entries: Vec::new() }
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}
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/// Add a workaround entry, merging with any existing entry at the same offset.
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pub fn add(&mut self, wa: Workaround) {
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if let Some(pos) = self.entries.iter().position(|e| e.offset == wa.offset) {
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let existing = &mut self.entries[pos];
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existing.set |= wa.set;
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existing.clear |= wa.clear;
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existing.read_mask |= wa.read_mask;
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info!("redox-drm-intel: merged workaround {} into existing entry at {:#06x}",
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wa.name, wa.offset);
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} else {
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// Maintain sorted order by offset for deterministic application.
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let pos = self.entries.binary_search_by_key(&wa.offset, |e| e.offset)
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.unwrap_or_else(|i| i);
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self.entries.insert(pos, wa);
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}
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}
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/// Apply all workarounds to the MMIO region.
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pub fn apply(&self, mmio: &MmioRegion) -> Result<u32> {
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let mut count = 0u32;
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for wa in &self.entries {
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if wa.clear == u32::MAX {
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// Write-only: no read, just write the value.
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mmio.write32(wa.offset, wa.set);
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} else if wa.masked {
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// Masked register: upper 16 bits = mask, lower 16 bits = value.
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mmio.write32(wa.offset, wa.set);
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} else {
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let old = mmio.read32(wa.offset);
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let val = (old & !wa.clear) | wa.set;
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if val != old || wa.clear == 0 {
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mmio.write32(wa.offset, val);
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}
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}
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count += 1;
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}
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info!("redox-drm-intel: applied {} {} workarounds", count, self.name);
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Ok(count)
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}
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/// Verify that all workarounds are still in effect.
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pub fn verify(&self, mmio: &MmioRegion) -> bool {
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let mut ok = true;
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for wa in &self.entries {
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if wa.read_mask == 0 {
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continue;
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}
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let cur = mmio.read32(wa.offset);
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let expected = (cur & wa.read_mask) | (wa.set & wa.read_mask);
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if (cur & wa.read_mask) != (wa.set & wa.read_mask) {
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log::error!("redox-drm-intel: workaround {} lost at {:#06x}! (got {:#010x}, expected {:#010x})",
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wa.name, wa.offset, cur, expected);
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ok = false;
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}
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}
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ok
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}
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}
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// ---------------------------------------------------------------------------
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// Helper macros for declarative workaround tables
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// ---------------------------------------------------------------------------
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/// `wa_masked_en(wal, offset, val)` — enable bits in a masked register.
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/// The value `val` is the field bits (lower 16). The macro computes the
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/// mask automatically as `(val << 16) | val`.
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#[inline]
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pub fn wa_masked_en(wal: &mut WorkaroundList, offset: usize, val: u32, name: &'static str) {
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let set = ((val & 0xFFFF) << 16) | (val & 0xFFFF);
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wal.add(Workaround { offset, clear: 0, set, read_mask: val, masked: true, name });
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}
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/// `wa_masked_dis(wal, offset, val)` — disable bits in a masked register.
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#[inline]
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pub fn wa_masked_dis(wal: &mut WorkaroundList, offset: usize, val: u32, name: &'static str) {
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let set = (val & 0xFFFF) << 16;
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wal.add(Workaround { offset, clear: 0, set, read_mask: val, masked: true, name });
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}
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/// `wa_masked_field_set(wal, offset, mask, val)` — set a specific field in a masked register.
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#[inline]
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pub fn wa_masked_field_set(wal: &mut WorkaroundList, offset: usize, mask: u32, val: u32, name: &'static str) {
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let set = ((mask & 0xFFFF) << 16) | (val & 0xFFFF);
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wal.add(Workaround { offset, clear: 0, set, read_mask: mask, masked: true, name });
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}
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/// `wa_write(wal, offset, val)` — full register write (read_mask = !0 for verification).
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#[inline]
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pub fn wa_write(wal: &mut WorkaroundList, offset: usize, val: u32, name: &'static str) {
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wal.add(Workaround { offset, clear: u32::MAX, set: val, read_mask: u32::MAX, masked: false, name });
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}
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/// `wa_write_or(wal, offset, val)` — read-modify-write OR.
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#[inline]
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pub fn wa_write_or(wal: &mut WorkaroundList, offset: usize, val: u32, name: &'static str) {
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wal.add(Workaround { offset, clear: 0, set: val, read_mask: val, masked: false, name });
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}
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/// `wa_write_clr(wal, offset, clr)` — read-modify-write clear.
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#[inline]
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pub fn wa_write_clr(wal: &mut WorkaroundList, offset: usize, clr: u32, name: &'static str) {
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wal.add(Workaround { offset, clear: clr, set: 0, read_mask: clr, masked: false, name });
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}
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/// `wa_write_clr_set(wal, offset, clr, set)` — read-modify-write clear then set.
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#[inline]
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pub fn wa_write_clr_set(wal: &mut WorkaroundList, offset: usize, clr: u32, set: u32, name: &'static str) {
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wal.add(Workaround { offset, clear: clr, set, read_mask: clr | set, masked: false, name });
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}
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/// `wa_add(wal, offset, clr, set, read_mask)` — generic RMW.
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#[inline]
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pub fn wa_add(wal: &mut WorkaroundList, offset: usize, clr: u32, set: u32, read_mask: u32, name: &'static str) {
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wal.add(Workaround { offset, clear: clr, set, read_mask, masked: false, name });
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}
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// ---------------------------------------------------------------------------
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// MCR (Multi-Cast Register) variants — used on Gen8+ for slice/subslice
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// specific registers. On Red Bear we treat them identically to regular
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// registers since we don't have MCR steering infrastructure yet.
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// ---------------------------------------------------------------------------
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#[inline]
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pub fn wa_mcr_masked_en(wal: &mut WorkaroundList, offset: usize, val: u32, name: &'static str) {
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wa_masked_en(wal, offset, val, name);
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}
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#[inline]
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pub fn wa_mcr_masked_dis(wal: &mut WorkaroundList, offset: usize, val: u32, name: &'static str) {
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wa_masked_dis(wal, offset, val, name);
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}
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#[inline]
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pub fn wa_mcr_write_or(wal: &mut WorkaroundList, offset: usize, val: u32, name: &'static str) {
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wa_write_or(wal, offset, val, name);
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}
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#[inline]
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pub fn wa_mcr_write_clr(wal: &mut WorkaroundList, offset: usize, clr: u32, name: &'static str) {
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wa_write_clr(wal, offset, clr, name);
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}
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#[inline]
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pub fn wa_mcr_write_clr_set(wal: &mut WorkaroundList, offset: usize, clr: u32, set: u32, name: &'static str) {
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wa_write_clr_set(wal, offset, clr, set, name);
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}
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#[inline]
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pub fn wa_mcr_masked_field_set(wal: &mut WorkaroundList, offset: usize, mask: u32, val: u32, name: &'static str) {
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wa_masked_field_set(wal, offset, mask, val, name);
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}
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// ---------------------------------------------------------------------------
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// Top-level dispatch: apply all GT workarounds for the detected generation.
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// ---------------------------------------------------------------------------
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pub fn build_gt_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList {
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let mut wal = WorkaroundList::new("GT");
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let gen = device_info.generation;
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let stepping = device_info.stepping;
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info!("redox-drm-intel: applying full workarounds for {:?} stepping={}", gen, stepping);
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info!("redox-drm-intel: building GT workarounds for {:?} stepping={}", gen, stepping);
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count += wa_gen9(mmio, gen);
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count += wa_gen9_5(mmio, gen);
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count += wa_gen12(mmio, gen, stepping);
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count += wa_gen12_7(mmio, gen);
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count += wa_xe2(mmio, gen, stepping);
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match gen {
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IntelGeneration::Gen4 => gen4_gt_workarounds_init(&mut wal),
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IntelGeneration::Gen4 => g4x_gt_workarounds_init(&mut wal),
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IntelGeneration::Gen5 => ilk_gt_workarounds_init(&mut wal),
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IntelGeneration::Gen6 => snb_gt_workarounds_init(&mut wal),
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IntelGeneration::Gen7 => ivb_gt_workarounds_init(&mut wal),
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IntelGeneration::Gen7 => hsw_gt_workarounds_init(&mut wal),
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IntelGeneration::Gen8 => gen8_gt_workarounds_init(&mut wal),
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IntelGeneration::Gen9 => gen9_gt_workarounds_init(&mut wal, stepping),
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IntelGeneration::Gen9_5 => gen9_gt_workarounds_init(&mut wal, stepping),
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IntelGeneration::Gen9_5 => icl_gt_workarounds_init(&mut wal),
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IntelGeneration::Gen12 => gen12_gt_workarounds_init(&mut wal, stepping),
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_ => {}
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}
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info!("redox-drm-intel: {} workarounds applied", count);
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info!("redox-drm-intel: {} GT workarounds built", wal.entries.len());
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wal
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}
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// ---------------------------------------------------------------------------
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// Generation-specific GT workaround tables (Gen4 – Gen12)
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// ---------------------------------------------------------------------------
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fn gen4_gt_workarounds_init(wal: &mut WorkaroundList) {
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/* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
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wa_masked_dis(wal, 0x0210, 1 << 12, "WaDisable_RenderCache_OperationalFlush");
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}
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fn g4x_gt_workarounds_init(wal: &mut WorkaroundList) {
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gen4_gt_workarounds_init(wal);
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/* WaDisableRenderCachePipelinedFlush:g4x,ilk */
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wa_masked_en(wal, 0x0210, 1 << 4, "WaDisableRenderCachePipelinedFlush");
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}
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fn ilk_gt_workarounds_init(wal: &mut WorkaroundList) {
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g4x_gt_workarounds_init(wal);
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wa_masked_en(wal, 0x20C4, 1 << 14, "Wa_3DChicken2_WM_Read_Pipelined");
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}
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fn snb_gt_workarounds_init(_wal: &mut WorkaroundList) {
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// No GT workarounds for Sandy Bridge.
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}
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fn ivb_gt_workarounds_init(wal: &mut WorkaroundList) {
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/* WaDisableRHWOOptimizationForRenderHang:ivb */
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wa_masked_dis(wal, 0x7018, 1 << 24, "WaDisableRHWOOptimizationForRenderHang");
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/* WaApplyL3ControlAndL3ChickenMode:ivb */
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wa_write(wal, 0xB01C, 0x7C000001, "WaApplyL3ControlAndL3ChickenMode_L3CNTL");
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wa_write(wal, 0xB024, 0x00FF0000, "WaApplyL3ControlAndL3ChickenMode_L3Chicken");
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/* WaForceL3Serialization:ivb */
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wa_write_clr(wal, 0xB034, 1 << 5, "WaForceL3Serialization");
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}
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fn hsw_gt_workarounds_init(wal: &mut WorkaroundList) {
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/* L3 caching of data atomics doesn't work -- disable it. */
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wa_write(wal, 0xB038, 1 << 16, "HSW_Scratch1_L3DataAtomicsDisable");
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wa_add(wal, 0xE4F0, 0, (1 << 31) | (1 << 31), 0, "HSW_ROW_CHICKEN3_L3GlobalAtomicsDisable");
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/* WaVSRefCountFullforceMissDisable:hsw */
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wa_write_clr(wal, 0x20A0, 1 << 5, "WaVSRefCountFullforceMissDisable");
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}
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fn gen8_gt_workarounds_init(wal: &mut WorkaroundList) {
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// Gen8 shares Gen9 workarounds in Linux; we apply the common subset here.
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// Most Gen8 workarounds are handled via context workarounds.
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}
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fn gen9_gt_workarounds_init(wal: &mut WorkaroundList, stepping: u8) {
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// Gen9 GT workarounds (also applies to BXT, KBL, GLK, CFL, CML).
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// Many Gen9 workarounds in Linux are context- or engine-specific;
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// the GT-level ones are relatively few.
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/* WaDisablePartialResolveInValue:gen9 */
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wa_masked_en(wal, 0xE4F0, 1 << 4, "WaDisablePartialResolveInValue");
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/* WaDisableRenderCachePipelinedFlush:gen9 */
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wa_masked_en(wal, 0xE180, 1 << 14, "WaDisableRenderCachePipelinedFlush");
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/* WaVFForcedNonCompressedBit:gen9 */
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wa_masked_en(wal, 0x7000, 1 << 3, "WaVFForcedNonCompressedBit");
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/* WaEnableChickenDCPR:gen9 */
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wa_masked_en(wal, 0x7004, 1 << 16, "WaEnableChickenDCPR");
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/* WaAllowUMDToModifySamplerMode:gen9 */
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wa_write(wal, 0xB11C, (1 << 2) | (1 << 31), "WaAllowUMDToModifySamplerMode");
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/* WaSetL3FreeList:gen9 */
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wa_write(wal, 0x00A0, 0x0080_0080 | (1 << 0), "WaSetL3FreeList");
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/* WaDisableRowChicken:gen9 */
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wa_masked_en(wal, 0xE4F0, 1 << 11, "WaDisableRowChicken");
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if stepping == 0 {
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/* Wa_22010751155:gen9_a0 */
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wa_write_or(wal, 0x7300, 1 << 8, "Wa_22010751155");
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}
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}
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fn icl_gt_workarounds_init(wal: &mut WorkaroundList) {
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// Gen11 (ICL) inherits Gen9 workarounds.
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gen9_gt_workarounds_init(wal, 0);
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/* WaForwardProgressSoftReset:icl */
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wa_write_or(wal, 0xD50, 1 << 2, "WaForwardProgressSoftReset");
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/* Wa_1806527549:icl */
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wa_write_clr(wal, 0xA18C, 1 << 2, "Wa_1806527549");
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}
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fn gen12_gt_workarounds_init(wal: &mut WorkaroundList, stepping: u8) {
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// Gen12 inherits Gen9 workarounds plus additional ones.
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gen9_gt_workarounds_init(wal, stepping);
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/* Wa_14017192718:gen12 */
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wa_write_or(wal, 0xA18C, 1 << 8, "Wa_14017192718");
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/* Wa_14012688713:gen12 */
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wa_write_or(wal, 0xA18C, 1 << 9, "Wa_14012688713");
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/* Wa_16013039831:gen12 */
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wa_masked_en(wal, 0xE4F0, 1 << 11, "Wa_16013039831");
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/* Wa_14013676891:gen12 */
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wa_write_or(wal, 0xB11C, 1 << 8, "Wa_14013676891");
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/* Wa_16012751909:gen12 */
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wa_write_or(wal, 0x55B0, (1 << 9) | (1 << 12), "Wa_16012751909");
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/* Wa_16012322899:gen12 */
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wa_write_or(wal, 0xE180, 1 << 14, "Wa_16012322899");
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if stepping == 0 {
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/* Wa_16012650089:gen12_a0 */
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wa_write_or(wal, 0x7300, 1 << 8, "Wa_16012650089");
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}
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}
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// ---------------------------------------------------------------------------
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// Context workaround tables (Gen6 – Gen12)
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// ---------------------------------------------------------------------------
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pub fn build_ctx_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList {
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let mut wal = WorkaroundList::new("context");
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let gen = device_info.generation;
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info!("redox-drm-intel: building context workarounds for {:?}", gen);
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match gen {
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IntelGeneration::Gen6 => gen6_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen7 => gen7_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen7 => gen7_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen8 => gen8_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen9 => gen9_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen9_5 => gen9_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen9_5 => icl_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen12 => gen12_ctx_workarounds_init(&mut wal),
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_ => {}
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}
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wal
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}
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fn gen6_ctx_workarounds_init(wal: &mut WorkaroundList) {
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||||
/* WaDisable_RenderCache_OperationalFlush:gen6 */
|
||||
wa_masked_dis(wal, 0x0210, 1 << 12, "WaDisable_RenderCache_OperationalFlush");
|
||||
}
|
||||
|
||||
fn gen7_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
/* WaDisableRHWOOptimizationForRenderHang:ivb */
|
||||
wa_masked_dis(wal, 0x7018, 1 << 24, "WaDisableRHWOOptimizationForRenderHang_ctx");
|
||||
|
||||
/* WaApplyL3ControlAndL3ChickenMode:ivb */
|
||||
wa_write(wal, 0xB01C, 0x7C000001, "WaApplyL3ControlAndL3ChickenMode_ctx");
|
||||
wa_write(wal, 0xB024, 0x00FF0000, "WaApplyL3ControlAndL3ChickenMode_ctx2");
|
||||
|
||||
/* WaForceL3Serialization:ivb */
|
||||
wa_write_clr(wal, 0xB034, 1 << 5, "WaForceL3Serialization_ctx");
|
||||
}
|
||||
|
||||
fn gen8_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
/* WaDisableRenderCachePipelinedFlush:bdw, chv */
|
||||
wa_masked_en(wal, 0xE180, 1 << 14, "WaDisableRenderCachePipelinedFlush_ctx");
|
||||
|
||||
/* WaVFForcedNonCompressedBit:bdw, chv */
|
||||
wa_masked_en(wal, 0x7000, 1 << 3, "WaVFForcedNonCompressedBit_ctx");
|
||||
|
||||
/* WaEnableChickenDCPR:bdw, chv */
|
||||
wa_masked_en(wal, 0x7004, 1 << 16, "WaEnableChickenDCPR_ctx");
|
||||
|
||||
/* WaDisablePartialResolveInValue:bdw, chv */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 4, "WaDisablePartialResolveInValue_ctx");
|
||||
|
||||
/* WaSetL3FreeList:bdw */
|
||||
wa_write(wal, 0x00A0, 0x0080_0080 | (1 << 0), "WaSetL3FreeList_ctx");
|
||||
|
||||
/* WaDisableRowChicken:bdw */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 11, "WaDisableRowChicken_ctx");
|
||||
}
|
||||
|
||||
fn gen9_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
/* Gen9 context workarounds are extensive in Linux (~130 entries).
|
||||
* We port the most critical ones here; the full table would require
|
||||
* resolving many engine-relative register constants.
|
||||
*/
|
||||
|
||||
/* WaDisableRenderCachePipelinedFlush:gen9 */
|
||||
wa_masked_en(wal, 0xE180, 1 << 14, "WaDisableRenderCachePipelinedFlush_ctx9");
|
||||
|
||||
/* WaVFForcedNonCompressedBit:gen9 */
|
||||
wa_masked_en(wal, 0x7000, 1 << 3, "WaVFForcedNonCompressedBit_ctx9");
|
||||
|
||||
/* WaEnableChickenDCPR:gen9 */
|
||||
wa_masked_en(wal, 0x7004, 1 << 16, "WaEnableChickenDCPR_ctx9");
|
||||
|
||||
/* WaDisablePartialResolveInValue:gen9 */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 4, "WaDisablePartialResolveInValue_ctx9");
|
||||
|
||||
/* WaSetL3FreeList:gen9 */
|
||||
wa_write(wal, 0x00A0, 0x0080_0080 | (1 << 0), "WaSetL3FreeList_ctx9");
|
||||
|
||||
/* WaDisableRowChicken:gen9 */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 11, "WaDisableRowChicken_ctx9");
|
||||
|
||||
/* Wa_1406298297:gen9 */
|
||||
wa_write_or(wal, 0x7300, 1 << 2, "Wa_1406298297");
|
||||
|
||||
/* Wa_1603948317:gen9 */
|
||||
wa_write_or(wal, 0x7304, 1 << 4, "Wa_1603948317");
|
||||
|
||||
/* Wa_18010453938:gen9 */
|
||||
wa_masked_en(wal, 0x55B0, 1 << 9, "Wa_18010453938");
|
||||
}
|
||||
|
||||
fn icl_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
// Gen11 context workarounds.
|
||||
gen9_ctx_workarounds_init(wal);
|
||||
|
||||
/* Wa_1409600907:icl */
|
||||
wa_write_or(wal, 0xA18C, 1 << 8, "Wa_1409600907");
|
||||
|
||||
/* Wa_16012727105:icl */
|
||||
wa_write_or(wal, 0xA18C, 1 << 9, "Wa_16012727105");
|
||||
}
|
||||
|
||||
fn gen12_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
// Gen12 context workarounds.
|
||||
gen9_ctx_workarounds_init(wal);
|
||||
|
||||
/* Wa_14014947963:gen12 */
|
||||
wa_masked_field_set(wal, 0x7A10, 0xFFFF, 0x4000, "Wa_14014947963");
|
||||
|
||||
/* Wa_16013271637:gen12 */
|
||||
wa_mcr_masked_en(wal, 0x7300, 1 << 8, "Wa_16013271637");
|
||||
|
||||
/* Wa_18019627453:gen12 */
|
||||
wa_mcr_masked_en(wal, 0x7A18, 1 << 4, "Wa_18019627453");
|
||||
|
||||
/* Wa_18018764978:gen12 */
|
||||
wa_mcr_masked_en(wal, 0x7A1C, 1 << 8, "Wa_18018764978");
|
||||
|
||||
/* Wa_18019271663:gen12 */
|
||||
wa_masked_en(wal, 0x7008, 1 << 16, "Wa_18019271663");
|
||||
|
||||
/* Wa_14019877138:gen12 */
|
||||
wa_mcr_masked_en(wal, 0x7A20, 1 << 4, "Wa_14019877138");
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Engine workaround tables
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
pub fn build_engine_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList {
|
||||
let mut wal = WorkaroundList::new("engine");
|
||||
let gen = device_info.generation;
|
||||
|
||||
info!("redox-drm-intel: building engine workarounds for {:?}", gen);
|
||||
|
||||
match gen {
|
||||
IntelGeneration::Gen9 | IntelGeneration::Gen9_5 |
|
||||
IntelGeneration::Gen9_5 | IntelGeneration::Gen12 => {
|
||||
general_render_compute_wa_init(&mut wal);
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
|
||||
wal
|
||||
}
|
||||
|
||||
fn general_render_compute_wa_init(wal: &mut WorkaroundList) {
|
||||
/* Wa_16013039831 */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 11, "Wa_16013039831_engine");
|
||||
|
||||
/* Wa_14013676891 */
|
||||
wa_write_or(wal, 0xB11C, 1 << 8, "Wa_14013676891_engine");
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Whitelist tables (register non-privilege access for userspace)
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
pub fn build_whitelist(device_info: &IntelDeviceInfo) -> WorkaroundList {
|
||||
let mut wal = WorkaroundList::new("whitelist");
|
||||
let gen = device_info.generation;
|
||||
|
||||
info!("redox-drm-intel: building whitelist for {:?}", gen);
|
||||
|
||||
match gen {
|
||||
IntelGeneration::Gen9 | IntelGeneration::Gen9_5 => gen9_whitelist_build(&mut wal),
|
||||
IntelGeneration::Gen9_5 => icl_whitelist_build(&mut wal),
|
||||
IntelGeneration::Gen12 => gen12_whitelist_build(&mut wal),
|
||||
_ => {}
|
||||
}
|
||||
|
||||
wal
|
||||
}
|
||||
|
||||
fn gen9_whitelist_build(wal: &mut WorkaroundList) {
|
||||
// Gen9 whitelist: registers that userspace is allowed to access directly.
|
||||
wa_add(wal, 0xA2C0, 0, 0, 0, "GEN9_SLICE_COMMON_ECO_CHICKEN");
|
||||
wa_add(wal, 0x7018, 0, 0, 0, "GEN7_COMMON_SLICE_CHICKEN1");
|
||||
wa_add(wal, 0xB01C, 0, 0, 0, "GEN7_L3CNTLREG1");
|
||||
wa_add(wal, 0xB024, 0, 0, 0, "GEN7_L3_CHICKEN_MODE");
|
||||
wa_add(wal, 0xB034, 0, 0, 0, "GEN7_L3SQCREG4");
|
||||
wa_add(wal, 0x7300, 0, 0, 0, "GEN7_HALF_SLICE_CHICKEN1");
|
||||
wa_add(wal, 0x7304, 0, 0, 0, "GEN7_HALF_SLICE_CHICKEN2");
|
||||
wa_add(wal, 0xE4F0, 0, 0, 0, "GEN7_ROW_CHICKEN");
|
||||
wa_add(wal, 0xE180, 0, 0, 0, "GEN7_HALF_SLICE_CHICKEN");
|
||||
wa_add(wal, 0x7000, 0, 0, 0, "CACHE_MODE_0");
|
||||
wa_add(wal, 0x7004, 0, 0, 0, "CACHE_MODE_1");
|
||||
wa_add(wal, 0xB11C, 0, 0, 0, "GEN9_SAMPLER_MODE");
|
||||
}
|
||||
|
||||
fn icl_whitelist_build(wal: &mut WorkaroundList) {
|
||||
gen9_whitelist_build(wal);
|
||||
// Gen11 additional whitelist entries.
|
||||
wa_add(wal, 0xA18C, 0, 0, 0, "GEN11_GT_SCRATCH");
|
||||
}
|
||||
|
||||
fn gen12_whitelist_build(wal: &mut WorkaroundList) {
|
||||
gen9_whitelist_build(wal);
|
||||
// Gen12 additional whitelist entries.
|
||||
wa_add(wal, 0x55B0, 0, 0, 0, "GEN12_COMMON_SLICE_CHICKEN2");
|
||||
wa_add(wal, 0x7A10, 0, 0, 0, "GEN12_VF_PREEMPTION");
|
||||
wa_add(wal, 0x7A18, 0, 0, 0, "GEN12_VFLSKPD");
|
||||
wa_add(wal, 0x7A1C, 0, 0, 0, "GEN12_PSS_MODE2");
|
||||
wa_add(wal, 0x7A20, 0, 0, 0, "GEN12_PSS_CHICKEN");
|
||||
wa_add(wal, 0x7008, 0, 0, 0, "GEN12_CACHE_MODE_1");
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Legacy top-level function kept for compatibility with existing driver init.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
pub fn apply_full_workarounds(mmio: &MmioRegion, device_info: &IntelDeviceInfo) -> u32 {
|
||||
let gt_wal = build_gt_workarounds(device_info);
|
||||
let ctx_wal = build_ctx_workarounds(device_info);
|
||||
let eng_wal = build_engine_workarounds(device_info);
|
||||
|
||||
let mut count = 0u32;
|
||||
count += gt_wal.apply(mmio).unwrap_or(0);
|
||||
count += ctx_wal.apply(mmio).unwrap_or(0);
|
||||
count += eng_wal.apply(mmio).unwrap_or(0);
|
||||
|
||||
info!("redox-drm-intel: {} total workarounds applied", count);
|
||||
count
|
||||
}
|
||||
|
||||
fn wa_gen9(mmio: &MmioRegion, gen: IntelGeneration) -> u32 {
|
||||
if !matches!(gen, IntelGeneration::Gen9) { return 0; }
|
||||
let mut c: u32 = 0;
|
||||
|
||||
let val = mmio.read32(0xE4F0); mmio.write32(0xE4F0, val | (1 << 4)); c += 1;
|
||||
let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
|
||||
let cm0 = mmio.read32(0x7000); mmio.write32(0x7000, cm0 | (1 << 3)); c += 1;
|
||||
let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
|
||||
let l3cfg = mmio.read32(0xB11C);
|
||||
mmio.write32(0xB11C, l3cfg | (1 << 2)); c += 1;
|
||||
mmio.write32(0xA0, 0x0080_0080 | (1 << 0)); c += 1;
|
||||
let row_ch = mmio.read32(0xE4F0);
|
||||
mmio.write32(0xE4F0, row_ch | (1 << 11)); c += 1;
|
||||
|
||||
c
|
||||
}
|
||||
|
||||
fn wa_gen9_5(mmio: &MmioRegion, gen: IntelGeneration) -> u32 {
|
||||
if !matches!(gen, IntelGeneration::Gen9_5) { return 0; }
|
||||
let mut c: u32 = 0;
|
||||
|
||||
let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
|
||||
let cm0 = mmio.read32(0x7000); mmio.write32(0x7000, cm0 | (1 << 3)); c += 1;
|
||||
let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
|
||||
let csc2 = mmio.read32(0x55B0); mmio.write32(0x55B0, csc2 | (1 << 9)); c += 1;
|
||||
let l3cfg = mmio.read32(0xB11C); mmio.write32(0xB11C, l3cfg | (1 << 8)); c += 1;
|
||||
let row_ch = mmio.read32(0xE4F0);
|
||||
mmio.write32(0xE4F0, row_ch | (1 << 4) | (1 << 11)); c += 1;
|
||||
mmio.write32(0xA0, 0x0080_0080 | (1 << 0)); c += 1;
|
||||
|
||||
c
|
||||
}
|
||||
|
||||
fn wa_gen12(mmio: &MmioRegion, gen: IntelGeneration, stepping: u8) -> u32 {
|
||||
if !matches!(gen, IntelGeneration::Gen12) { return 0; }
|
||||
let mut c: u32 = 0;
|
||||
|
||||
let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
|
||||
let l3cfg = mmio.read32(0xB11C); mmio.write32(0xB11C, l3cfg | (1 << 8)); c += 1;
|
||||
let csc2 = mmio.read32(0x55B0); mmio.write32(0x55B0, csc2 | (1 << 9) | (1 << 12)); c += 1;
|
||||
let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
|
||||
let row_ch = mmio.read32(0xE4F0);
|
||||
mmio.write32(0xE4F0, row_ch | (1 << 4) | (1 << 11)); c += 1;
|
||||
|
||||
if stepping == 0 {
|
||||
let chk = mmio.read32(0x7300); mmio.write32(0x7300, chk | (1 << 8)); c += 1;
|
||||
}
|
||||
|
||||
let cache_mode_0 = mmio.read32(0x7000);
|
||||
mmio.write32(0x7000, cache_mode_0 | (1 << 3)); c += 1;
|
||||
|
||||
c
|
||||
}
|
||||
|
||||
fn wa_gen12_7(mmio: &MmioRegion, gen: IntelGeneration) -> u32 {
|
||||
if !matches!(gen, IntelGeneration::Gen12_7) { return 0; }
|
||||
let mut c: u32 = 0;
|
||||
|
||||
let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
|
||||
let l3cfg = mmio.read32(0xB11C); mmio.write32(0xB11C, l3cfg | (1 << 8)); c += 1;
|
||||
let csc2 = mmio.read32(0x55B0); mmio.write32(0x55B0, csc2 | (1 << 9) | (1 << 12) | (1 << 15)); c += 1;
|
||||
let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
|
||||
let row_ch = mmio.read32(0xE4F0);
|
||||
mmio.write32(0xE4F0, row_ch | (1 << 4) | (1 << 11)); c += 1;
|
||||
|
||||
c
|
||||
}
|
||||
|
||||
fn wa_xe2(mmio: &MmioRegion, gen: IntelGeneration, stepping: u8) -> u32 {
|
||||
if !matches!(gen, IntelGeneration::GenXe2) { return 0; }
|
||||
let mut c: u32 = 0;
|
||||
|
||||
let cm1 = mmio.read32(0x7004); mmio.write32(0x7004, cm1 | (1 << 16)); c += 1;
|
||||
let l3cfg = mmio.read32(0xB11C); mmio.write32(0xB11C, l3cfg | (1 << 8) | (1 << 16)); c += 1;
|
||||
let csc2 = mmio.read32(0x55B0);
|
||||
mmio.write32(0x55B0, csc2 | (1 << 9) | (1 << 12) | (1 << 15) | (1 << 18)); c += 1;
|
||||
let hsc2 = mmio.read32(0xE180); mmio.write32(0xE180, hsc2 | (1 << 14)); c += 1;
|
||||
let row_ch = mmio.read32(0xE4F0);
|
||||
mmio.write32(0xE4F0, row_ch | (1 << 4) | (1 << 11)); c += 1;
|
||||
|
||||
if stepping == 0 {
|
||||
let chk = mmio.read32(0x7300); mmio.write32(0x7300, chk | (1 << 8) | (1 << 16)); c += 1;
|
||||
}
|
||||
|
||||
c
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user