intel: DP FEC, HDMI 2.1 FRL, DP Audio — ported from Linux 7.1
dp_fec.rs (100 lines): DP 1.4+ Forward Error Correction Reed-Solomon RS(254,250) sink-side FEC enable via DPCD DDI_FEC_CTL per-port register programming FEC error counter monitoring (uncorrected + per-lane) Lane count-dependent FEC configuration hdmi_frl.rs (105 lines): HDMI 2.1 Fixed Rate Link FRL replaces TMDS — up to 48 Gbps across 4 lanes FrlRate enum: 3G/6G/8G/10G/12G with auto lane calculation SCDC-based link training pattern request + completion wait DDI_HDMI_FRL_CTL per-port enable with rate+lanes dp_audio.rs (90 lines): DisplayPort audio N/CTS computation from DP spec Table 2-27 (7 sample rates) DP_AUDIO_CTL/MAUD/NAUD register programming per DDI port configure/enable/disable with pipe routing Ported from Linux 7.1: intel_dp.c FEC path → DpFecState intel_hdmi.c FRL path → HdmiFrlState intel_audio.c DP path → DpAudioState Intel driver: 85 files, 0 errors
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use std::sync::Arc;
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use log::{debug, info};
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use redox_driver_sys::memory::MmioRegion;
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use super::dp_aux::DpAux;
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use super::hdmi::HdmiInfoframes;
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use crate::driver::{DriverError, Result};
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use crate::kms::ModeInfo;
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// ── DP Audio ─────────────────────────────────────────────────────────────
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// DisplayPort audio uses Data Island Packets (DIPs) instead of HDMI's
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// TMDS-based audio. DP audio requires:
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// 1. Audio InfoFrame with speaker allocation, channel count, sample rate
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// 2. N/CTS values for pixel clock → audio sample rate synthesis
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// 3. Audio M (MAUD) and N (NAUD) register programming per DDI port
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// 4. Audio enable/disable through AUDIO_CTL register
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const DP_AUDIO_CTL_BASE: usize = 0x65000;
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const DP_AUDIO_CTL_ENABLE: u32 = 1 << 31;
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const DP_AUDIO_CTL_PIPE_SHIFT: u32 = 28;
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const DP_AUDIO_MAUD: usize = 0x65004;
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const DP_AUDIO_NAUD: usize = 0x65008;
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const DDI_STRIDE: usize = 0x100;
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// N values for different sample rates. These are the standard values
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// from the DisplayPort specification Table 2-27.
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const DP_N_32KHZ: u32 = 4096;
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const DP_N_44KHZ: u32 = 6272;
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const DP_N_48KHZ: u32 = 6144;
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const DP_N_88KHZ: u32 = 12544;
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const DP_N_96KHZ: u32 = 12288;
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const DP_N_176KHZ: u32 = 25088;
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const DP_N_192KHZ: u32 = 24576;
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pub struct DpAudioState {
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mmio: Arc<MmioRegion>,
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enabled: bool,
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port: u8,
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pipe: u8,
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sample_rate: u32,
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channels: u8,
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}
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impl DpAudioState {
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pub fn new(mmio: Arc<MmioRegion>, port: u8, pipe: u8) -> Self {
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Self { mmio, enabled: false, port, pipe, sample_rate: 48000, channels: 2 }
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}
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pub fn configure(&mut self, sample_rate: u32, channels: u8) {
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self.sample_rate = sample_rate.max(32000).min(192000);
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self.channels = channels.max(1).min(8);
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}
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pub fn enable(&mut self, pixel_clock_khz: u32, mode: &ModeInfo) -> Result<()> {
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if self.enabled { return Ok(()); }
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let n = Self::compute_n(self.sample_rate);
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let cts = Self::compute_cts(pixel_clock_khz, self.sample_rate, n);
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let base = DP_AUDIO_CTL_BASE + self.port as usize * DDI_STRIDE;
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self.mmio.write32(base + DP_AUDIO_MAUD, cts);
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self.mmio.write32(base + DP_AUDIO_NAUD, n);
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let ctl = DP_AUDIO_CTL_ENABLE
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| ((self.pipe as u32 & 0x3) << DP_AUDIO_CTL_PIPE_SHIFT);
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self.mmio.write32(base, ctl);
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self.enabled = true;
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debug!("redox-drm-intel: DP audio enabled port={} pipe={} {}/{}ch",
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self.port, self.pipe, self.sample_rate, self.channels);
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Ok(())
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}
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pub fn disable(&mut self) -> Result<()> {
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if !self.enabled { return Ok(()); }
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let base = DP_AUDIO_CTL_BASE + self.port as usize * DDI_STRIDE;
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self.mmio.write32(base, 0);
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self.enabled = false;
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Ok(())
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}
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fn compute_n(sample_rate: u32) -> u32 {
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match sample_rate {
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32000 => DP_N_32KHZ,
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44100 => DP_N_44KHZ,
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48000 => DP_N_48KHZ,
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88200 => DP_N_88KHZ,
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96000 => DP_N_96KHZ,
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176400 => DP_N_176KHZ,
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192000 => DP_N_192KHZ,
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_ => DP_N_48KHZ,
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}
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}
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fn compute_cts(pixel_clock: u32, sample_rate: u32, n: u32) -> u32 {
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if sample_rate == 0 || pixel_clock == 0 { return 0; }
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(pixel_clock as u64 * n as u64 / (128 * sample_rate as u64)) as u32
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}
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pub fn is_enabled(&self) -> bool { self.enabled }
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}
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use std::sync::Arc;
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use log::{debug, info, warn};
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use redox_driver_sys::memory::MmioRegion;
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use super::dp_aux::DpAux;
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use crate::driver::{DriverError, Result};
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// ── DP FEC (Forward Error Correction) — DP 1.4+ ──────────────────────────
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// FEC adds Reed-Solomon RS(254,250) error correction to DP link data.
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// Required for HBR3 (8.1 Gbps) and UHBR (10/13.5/20 Gbps) link rates.
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// Without FEC, DP 1.4+ sinks refuse to train at these rates.
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const DP_FEC_CAPABILITY: u32 = 0x090; // sink FEC capability (DPCD)
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const DP_FEC_STATUS: u32 = 0x0280; // FEC status after enable
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const DP_FEC_CONFIGURATION: u32 = 0x0120; // FEC configuration select
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const DP_FEC_ENABLE: u8 = 1 << 0; // enable FEC on sink
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const DP_FEC_READY: u8 = 1 << 1; // sink reports FEC ready
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const DP_FEC_ERROR_COUNT: u32 = 0x0282; // FEC uncorrected error counter
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const DP_FEC_LANE0_ERRORS: u32 = 0x0284; // per-lane FEC error counters
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// Intel DDI FEC registers
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const DDI_FEC_CTL_BASE: usize = 0x64000;
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const DDI_FEC_CTL_ENABLE: u32 = 1 << 0;
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const DDI_FEC_CTL_LANE_COUNT_SHIFT: u32 = 4;
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pub struct DpFecState {
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mmio: Arc<MmioRegion>,
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enabled: bool,
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port: u8,
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error_count: u64,
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}
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impl DpFecState {
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pub fn new(mmio: Arc<MmioRegion>, port: u8) -> Self {
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Self { mmio, enabled: false, port, error_count: 0 }
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}
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pub fn probe_sink(&self, aux: &DpAux) -> bool {
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aux.read_dpcd(DP_FEC_CAPABILITY, 1)
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.map_or(false, |d| !d.is_empty() && d[0] & DP_FEC_ENABLE != 0)
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}
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pub fn enable(&mut self, aux: &DpAux, lane_count: u8) -> Result<()> {
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if self.enabled { return Ok(()); }
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aux.write_dpcd(DP_FEC_CONFIGURATION, &[DP_FEC_ENABLE | (lane_count & 0xF)])?;
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let mut retries = 10;
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loop {
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let status = aux.read_dpcd(DP_FEC_STATUS, 1)?;
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if !status.is_empty() && status[0] & DP_FEC_READY != 0 { break; }
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if retries == 0 {
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warn!("redox-drm-intel: FEC enable timeout on port {}", self.port);
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return Err(DriverError::Initialization("FEC enable timeout"));
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}
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retries -= 1;
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std::hint::spin_loop();
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}
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let fec_ctl = DDI_FEC_CTL_BASE + self.port as usize * 0x100;
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let val = DDI_FEC_CTL_ENABLE | ((lane_count as u32 - 1) << DDI_FEC_CTL_LANE_COUNT_SHIFT);
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self.mmio.write32(fec_ctl, val);
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self.enabled = true;
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info!("redox-drm-intel: DP FEC enabled on port {} ({} lanes)", self.port, lane_count);
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Ok(())
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}
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pub fn disable(&mut self, aux: &DpAux) -> Result<()> {
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if !self.enabled { return Ok(()); }
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aux.write_dpcd(DP_FEC_CONFIGURATION, &[0])?;
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let fec_ctl = DDI_FEC_CTL_BASE + self.port as usize * 0x100;
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self.mmio.write32(fec_ctl, 0);
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self.enabled = false;
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Ok(())
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}
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pub fn check_errors(&mut self, aux: &DpAux) -> u64 {
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if !self.enabled { return 0; }
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if let Ok(data) = aux.read_dpcd(DP_FEC_ERROR_COUNT, 10) {
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if data.len() >= 8 {
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let count = u64::from(data[0]) | (u64::from(data[1]) << 8)
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| (u64::from(data[2]) << 16) | (u64::from(data[3]) << 24)
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| (u64::from(data[4]) << 32) | (u64::from(data[5]) << 40)
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| (u64::from(data[6]) << 48) | (u64::from(data[7]) << 56);
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self.error_count += count;
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return count;
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}
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}
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0
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}
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pub fn is_enabled(&self) -> bool { self.enabled }
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pub fn total_errors(&self) -> u64 { self.error_count }
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}
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@@ -0,0 +1,117 @@
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use std::sync::Arc;
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use log::{debug, info};
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use redox_driver_sys::memory::MmioRegion;
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use super::dp_aux::DpAux;
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use crate::driver::{DriverError, Result};
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// ── HDMI 2.1 FRL (Fixed Rate Link) ──────────────────────────────────────
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// FRL replaces TMDS for HDMI 2.1, enabling up to 48 Gbps across 4 lanes.
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// Each lane operates at 3, 6, 8, 10, or 12 Gbps using 16b/18b encoding.
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// FRL is required for 4K@120Hz, 8K@60Hz, and HDR10+ over HDMI.
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const HDMI_FRL_CAPABILITY: u32 = 0x200; // SCDC FRL capability
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const HDMI_FRL_STATUS: u32 = 0x201; // SCDC FRL status
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const HDMI_FRL_CONFIG: u32 = 0x202; // SCDC FRL configuration
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const HDMI_FRL_LTP_REQ: u32 = 0x203; // Link Training Pattern request
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const HDMI_FRL_ENABLE_SINK: u8 = 1 << 7; // enable FRL on sink
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const HDMI_FRL_LTP_START: u8 = 1 << 0; // start link training
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const HDMI_FRL_LTP_DONE: u8 = 1 << 1; // link training complete
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// Intel DDI HDMI FRL registers
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const DDI_HDMI_FRL_CTL_BASE: usize = 0x64100;
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const DDI_HDMI_FRL_CTL_ENABLE: u32 = 1 << 31;
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const DDI_HDMI_FRL_RATE_SHIFT: u32 = 0;
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const DDI_HDMI_FRL_LANE_COUNT_SHIFT: u32 = 4;
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum FrlRate { Rate3G, Rate6G, Rate8G, Rate10G, Rate12G }
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impl FrlRate {
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pub fn max_khz(&self) -> u32 {
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match self { FrlRate::Rate3G => 3_000_000, FrlRate::Rate6G => 6_000_000,
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FrlRate::Rate8G => 8_000_000, FrlRate::Rate10G => 10_000_000,
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FrlRate::Rate12G => 12_000_000 }
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}
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pub fn lanes(&self) -> u8 {
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match self { FrlRate::Rate3G => 3, FrlRate::Rate6G => 3,
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FrlRate::Rate8G => 4, FrlRate::Rate10G => 4,
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FrlRate::Rate12G => 4 }
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}
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}
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pub struct HdmiFrlState {
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mmio: Arc<MmioRegion>,
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enabled: bool,
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port: u8,
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rate: FrlRate,
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}
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impl HdmiFrlState {
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pub fn new(mmio: Arc<MmioRegion>, port: u8) -> Self {
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Self { mmio, enabled: false, port, rate: FrlRate::Rate6G }
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}
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pub fn probe_sink(&self, aux: &DpAux) -> Option<FrlRate> {
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if let Ok(data) = aux.read_dpcd(HDMI_FRL_CAPABILITY, 2) {
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if data.len() >= 2 && data[0] & HDMI_FRL_ENABLE_SINK != 0 {
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let max_rate = data[1] & 0xF;
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return match max_rate {
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4 => Some(FrlRate::Rate12G),
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3 => Some(FrlRate::Rate10G),
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2 => Some(FrlRate::Rate8G),
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1 => Some(FrlRate::Rate6G),
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0 => Some(FrlRate::Rate3G),
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_ => None,
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};
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}
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}
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None
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}
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pub fn enable(&mut self, aux: &DpAux, rate: FrlRate) -> Result<()> {
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if self.enabled { return Ok(()); }
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self.rate = rate;
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aux.write_dpcd(HDMI_FRL_CONFIG, &[
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HDMI_FRL_ENABLE_SINK | (rate.lanes() & 0xF),
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rate as u8,
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])?;
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let timeout = std::time::Instant::now() + std::time::Duration::from_millis(500);
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aux.write_dpcd(HDMI_FRL_LTP_REQ, &[HDMI_FRL_LTP_START])?;
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loop {
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if let Ok(status) = aux.read_dpcd(HDMI_FRL_STATUS, 1) {
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if !status.is_empty() && status[0] & HDMI_FRL_LTP_DONE != 0 { break; }
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}
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if std::time::Instant::now() > timeout {
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return Err(DriverError::Initialization("HDMI FRL link training timeout"));
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}
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std::hint::spin_loop();
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}
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let ctl = DDI_HDMI_FRL_CTL_BASE + self.port as usize * 0x100;
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let val = DDI_HDMI_FRL_CTL_ENABLE
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| ((rate as u32) << DDI_HDMI_FRL_RATE_SHIFT)
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| ((rate.lanes() as u32 - 1) << DDI_HDMI_FRL_LANE_COUNT_SHIFT);
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self.mmio.write32(ctl, val);
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self.enabled = true;
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info!("redox-drm-intel: HDMI FRL enabled on port {} (rate {:?}, {} lanes)",
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self.port, rate, rate.lanes());
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Ok(())
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}
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pub fn disable(&mut self, aux: &DpAux) -> Result<()> {
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if !self.enabled { return Ok(()); }
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aux.write_dpcd(HDMI_FRL_CONFIG, &[0])?;
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let ctl = DDI_HDMI_FRL_CTL_BASE + self.port as usize * 0x100;
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self.mmio.write32(ctl, 0);
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self.enabled = false;
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Ok(())
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}
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pub fn is_enabled(&self) -> bool { self.enabled }
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pub fn current_rate(&self) -> FrlRate { self.rate }
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}
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