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docs: update MASTER plan — add GPU/desktop progress section

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Added desktop/GPU progress section tracking VirGL 3D enablement
and Intel GPU DDI port register fixes. Removed resolved references
to KERNEL-IPC, SYSCALL-MIGRATION plans.

Desktop path: virtio-gpu VirGL negotiation enabled, Kaby Lake
DDI_BUF_CTL registers populated, Tiger Lake already works.
This commit is contained in:
vasilito
2026-07-09 12:53:10 +03:00
parent b9e53c500a
commit 8de5ae5184
1 changed files with 13 additions and 3 deletions
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local/docs/IMPLEMENTATION-MASTER-PLAN.md
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@@ -28,10 +28,20 @@ Subsystem plans resolved/no longer active:
| Plan | Status |
|------|--------|
| `IMPROVEMENT-PLAN.md` | **RESOLVED** — all 38 quality gaps verified/fixed |
| `KERNEL-IPC-CREDENTIAL-PLAN.md` | Resolved |
| `SYSCALL-MIGRATION-PLAN.md` | Resolved |
| `WAYLAND-IMPLEMENTATION-PLAN.md` | Resolved |
| `WIFI-IMPLEMENTATION-PLAN.md` | Resolved (iwlwifi driver complete) |
| `WAYLAND-IMPLEMENTATION-PLAN.md` | Resolved (Qt6 Wayland, Mesa, KWin building) |
| `USB-IMPLEMENTATION-PLAN.md` | Updated (P0+P1 done, class drivers functional, 12+ quirks) |
| `RAPL-IMPLEMENTATION-PLAN.md` | P0 resolved (MSR scheme), Phase 1 reader done |
| `ACPI-IMPROVEMENT-PLAN.md` | Updated (FADT fix, LegacyBackend basic) |
### Desktop/GPU Progress (2026-07-08)
| Driver | Status | Detail |
|--------|--------|--------|
| **virtio-gpu VirGL** | 3D feature negotiation enabled | `virtio_gpu_dri.so` builds (17.4MB), CommandTy has 10 3D commands |
| **ihdgd Kaby Lake** | DDI port registers populated | Gen9 DDI_BUF_CTL registers (0x64000-0x64300) for display output |
| **ihdgd Tiger Lake** | Port registers already set | Gen12 registers (0x162000, 0x6C000, 0x160000) |
| **Mesa virgl** | Builds | EGL runtime probe is remaining gap |
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