From 8de5ae518439679319472f176c109f15ec794845 Mon Sep 17 00:00:00 2001 From: vasilito Date: Thu, 9 Jul 2026 12:53:10 +0300 Subject: [PATCH] =?UTF-8?q?docs:=20update=20MASTER=20plan=20=E2=80=94=20ad?= =?UTF-8?q?d=20GPU/desktop=20progress=20section?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added desktop/GPU progress section tracking VirGL 3D enablement and Intel GPU DDI port register fixes. Removed resolved references to KERNEL-IPC, SYSCALL-MIGRATION plans. Desktop path: virtio-gpu VirGL negotiation enabled, Kaby Lake DDI_BUF_CTL registers populated, Tiger Lake already works. --- local/docs/IMPLEMENTATION-MASTER-PLAN.md | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/local/docs/IMPLEMENTATION-MASTER-PLAN.md b/local/docs/IMPLEMENTATION-MASTER-PLAN.md index f676e73528..4d3c82f6bb 100644 --- a/local/docs/IMPLEMENTATION-MASTER-PLAN.md +++ b/local/docs/IMPLEMENTATION-MASTER-PLAN.md @@ -28,10 +28,20 @@ Subsystem plans resolved/no longer active: | Plan | Status | |------|--------| | `IMPROVEMENT-PLAN.md` | **RESOLVED** — all 38 quality gaps verified/fixed | -| `KERNEL-IPC-CREDENTIAL-PLAN.md` | Resolved | -| `SYSCALL-MIGRATION-PLAN.md` | Resolved | -| `WAYLAND-IMPLEMENTATION-PLAN.md` | Resolved | | `WIFI-IMPLEMENTATION-PLAN.md` | Resolved (iwlwifi driver complete) | +| `WAYLAND-IMPLEMENTATION-PLAN.md` | Resolved (Qt6 Wayland, Mesa, KWin building) | +| `USB-IMPLEMENTATION-PLAN.md` | Updated (P0+P1 done, class drivers functional, 12+ quirks) | +| `RAPL-IMPLEMENTATION-PLAN.md` | P0 resolved (MSR scheme), Phase 1 reader done | +| `ACPI-IMPROVEMENT-PLAN.md` | Updated (FADT fix, LegacyBackend basic) | + +### Desktop/GPU Progress (2026-07-08) + +| Driver | Status | Detail | +|--------|--------|--------| +| **virtio-gpu VirGL** | 3D feature negotiation enabled | `virtio_gpu_dri.so` builds (17.4MB), CommandTy has 10 3D commands | +| **ihdgd Kaby Lake** | DDI port registers populated | Gen9 DDI_BUF_CTL registers (0x64000-0x64300) for display output | +| **ihdgd Tiger Lake** | Port registers already set | Gen12 registers (0x162000, 0x6C000, 0x160000) | +| **Mesa virgl** | Builds | EGL runtime probe is remaining gap | ---