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intel: remove incorrectly applied per-engine VDBOX workarounds from GT path

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Admin Pupkin
2026-06-03 09:35:04 +03:00
parent 428def66e3
commit 7c112e8863
1 changed files with 0 additions and 2 deletions
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local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs
-2
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@@ -377,7 +377,6 @@ fn gen12_gt_workarounds_init(wal: &mut WorkaroundList, stepping: u8) {
wa_write_or(wal, GEN8_SAMPLER_MODE, 1 << 8, "Wa_14013676891");
wa_write_or(wal, GEN12_COMMON_SLICE_CHICKEN2, GEN12_CSC2_SCOREBOARD_STALL_FLUSH_CONTROL, "Wa_16012751909");
wa_write_or(wal, GEN7_HALF_SLICE_CHICKEN1, GEN8_HSH_CHICKEN3_DOP_GATING_DISABLE, "Wa_16012322899");
wa_write_or(wal, VDBOX_CGCTL3F10, IECPUNIT_CLKGATE_DIS, "Wa_14011060649");
wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE, "Wa_14011059788");
wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, 0, 0, "Wa_14015795083");
wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329_render");
@@ -405,7 +404,6 @@ fn xelpg_gt_workarounds_init(wal: &mut WorkaroundList, _stepping: u8) {
}
fn xelpmp_gt_workarounds_init(wal: &mut WorkaroundList) {
wa_write_or(wal, VDBOX_CGCTL3F1C, MFXPIPE_CLKGATE_DIS, "Wa_16021867713");
wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB, "Wa_14018778641");
wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329_xelpmp");
wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE, "Wa_22016670082_xelpmp");