intel: fix DG2/xelpg context tuning register constants (RASTER_2, FF_MODE2, L3SQCREG5)

This commit is contained in:
2026-06-03 09:28:22 +03:00
parent 70c65b5a87
commit 52f589e31d
@@ -275,13 +275,13 @@ pub const XELPMP_VDBX_MOD_CTRL: usize = 0xB0F8;
pub const VDBOX_CGCTL3F10: usize = 0xB0FC;
pub const VDBOX_CGCTL3F1C: usize = 0xB100;
pub const GEN12_FF_MODE2: usize = 0x6604;
pub const XEHP_L3SQCREG5: usize = 0xB104;
pub const XEHP_L3SQCREG5: usize = 0xB158;
pub const XEHP_L3SCQREG7: usize = 0xB188;
pub const BLEND_FILL_CACHING_OPT_DIS: u32 = 1 << 3;
pub const XEHP_SQCM: usize = 0x8724;
pub const EN_32B_ACCESS: u32 = 1 << 30;
pub const XEHP_FF_MODE2: usize = 0xB108;
pub const CHICKEN_RASTER_2: usize = 0xB10C;
pub const XEHP_FF_MODE2: usize = 0x6604;
pub const CHICKEN_RASTER_2: usize = 0x6208;
pub const XEHP_SLICE_COMMON_ECO_CHICKEN1: usize = 0x731C;
pub const XEHP_PSS_MODE2: usize = 0x703C;
pub const XEHP_PSS_CHICKEN: usize = 0x7044;