intel: fix critical register constant errors (UNSLICE/SUBSLICE/SLICE CLKGATE offsets + bit values)

This commit is contained in:
2026-06-03 09:26:06 +03:00
parent 06b3c0b921
commit 70c65b5a87
@@ -256,11 +256,11 @@ pub const DFR_DISABLE: u32 = 1 << 9;
pub const GEN11_LSN_UNSLCVC: usize = 0xB018;
pub const GEN8_GAMW_ECO_DEV_RW_IA: usize = 0x4080;
pub const UNSLICE_UNIT_LEVEL_CLKGATE: usize = 0x9434;
pub const UNSLICE_UNIT_LEVEL_CLKGATE2: usize = 0x9438;
pub const GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE: usize = 0x943C;
pub const GEN11_SLICE_UNIT_LEVEL_CLKGATE: usize = 0x9440;
pub const SUBSLICE_UNIT_LEVEL_CLKGATE2: usize = 0x9444;
pub const VSUNIT_CLKGATE_DIS_TGL: usize = 0x9448;
pub const UNSLICE_UNIT_LEVEL_CLKGATE2: usize = 0x94E4;
pub const GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE: usize = 0x9524;
pub const GEN11_SLICE_UNIT_LEVEL_CLKGATE: usize = 0x94D4;
pub const SUBSLICE_UNIT_LEVEL_CLKGATE2: usize = 0x9528;
pub const VSUNIT_CLKGATE_DIS_TGL: u32 = 1 << 19;
pub const SARB_CHICKEN1: usize = 0xB01C;
pub const GEN7_MISCCPCTL: usize = 0x9488;
pub const RENDER_MOD_CTRL: usize = 0xB0D4;
@@ -349,10 +349,10 @@ pub const GAMW_ECO_DEV_CTX_RELOAD_DISABLE: u32 = 1 << 7;
pub const GAMT_CHKN_DISABLE_L3_COH_PIPE: u32 = 1 << 6;
pub const VSUNIT_CLKGATE_DIS: u32 = 1 << 20;
pub const HSUNIT_CLKGATE_DIS: u32 = 1 << 7;
pub const PSDUNIT_CLKGATE_DIS: u32 = 1 << 28;
pub const GWUNIT_CLKGATE_DIS: u32 = 1 << 18;
pub const L3_CLKGATE_DIS: u32 = 1 << 25;
pub const L3_CR2X_CLKGATE_DIS: u32 = 1 << 21;
pub const PSDUNIT_CLKGATE_DIS: u32 = 1 << 5;
pub const GWUNIT_CLKGATE_DIS: u32 = 1 << 16;
pub const L3_CLKGATE_DIS: u32 = 1 << 16;
pub const L3_CR2X_CLKGATE_DIS: u32 = 1 << 17;
pub const CPSSUNIT_CLKGATE_DIS: u32 = 1 << 4;
pub const CG3DDISCFEG_CLKGATE_DIS: u32 = 1 << 22;
pub const DSS_ROUTER_CLKGATE_DIS: u32 = 1 << 15;