vasilito ea727e673e intel: DPLL module header — architecture documentation ...

Document all 5 PLL architectures per generation:
  SKL/KBL/CFL: LCPLL1/2 + WRPLL1/2
  ICL: LCPLL1/2 + DPLL for MG/Combo PHY
  TGL/ADL: LCPLL1/2 + WRPLL + TGL CFGCR
  MTL: DPLL_CTRL1 + DPLL_FREQ
  Xe2: DPLL_CTRL1/2 with power enable

wrpll_compute() algorithm: 3 DCO central frequencies × 43 dividers
with deviation minimization + p0×p1×p2 decomposition

2026-06-02 11:10:51 +03:00

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intel: DPLL module header — architecture documentation

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AGENTS.md

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