c9b723c941
163 → 300 lines covering all supported generations: SKL (Gen9): LCPLL1/LCPLL2 + WRPLL1/WRPLL2 enable with lock polling DCO integer/fraction programming via WRPLL_CTL registers ICL (Gen11): DPLL_CFGCR0/CFGCR1 with frequency_enable + DCO/QDIV/KDIV/PDIV Dedicated CFGCR registers at 0x164284/0x164288 TGL/ADL/DG2 (Gen12): TGL-specific DPLL_CFGCR0/CFGCR1 at 0x164294/0x164298 Link rate selection (HBR2/HBR3) MTL (Gen12.7): DPLL_CTRL1/DPLL_FREQ register programming DCO integer/fraction packed into single frequency register Xe2 (ARL/LNL/BMG): DPLL_CTRL1/CTRL2 with POWER_ENABLE + ENABLE bits New DpllConfig with: pll_id, dco_int, dco_frac, pdiv/qdiv/kdiv vco_khz() computed from refclk * kdiv / (pdiv * qdiv) get_pll_for_clock() with config search + program + active tracking release_pll() for connector hot-unplug cleanup next_available_pll() automatic allocation across 4+ PLLs