redox-drm Intel: implement EDID I2C/DDC reading via GMBUS
Replaced the 'EDID I2C/DDC not yet implemented' stub with a real
Intel GMBUS controller implementation for reading EDID blocks from
connected displays.
Added GMBUS register definitions (Intel PRM Display chapter):
- GMBUS0 (0xC5100): pin pair select (DDC=3), rate (100kHz)
- GMBUS1 (0xC5104): SW_RDY, CYCLE_WAIT, CYCLE_INDEX, size, addr
- GMBUS2 (0xC5108): HW_RDY, ACTIVE, INUSE status bits
- GMBUS3 (0xC510C): 32-bit data register
- GMBUS4 (0xC5110): interrupt mask
Implemented gmbus_read() helper:
1. Selects DDC pin pair at 100kHz
2. Programs GMBUS1 with SW_RDY | CYCLE_WAIT | CYCLE_INDEX,
transfer size, EDID block offset index, and I2C slave address
3. Polls GMBUS2 for HW_RDY (100k iteration timeout)
4. Reads data words from GMBUS3 into output buffer
5. Stops cycle via GMBUS1 SW_RDY | CYCLE_STOP
read_edid_block() delegates to gmbus_read() with slave=0x50
(standard EDID address) and offset=block*128.
Previously: synthetic 1024x768 EDID fallback on all connectors.
Now: attempts real EDID read via GMBUS, falls back to synthetic
if GMBUS read fails (display disconnected or I2C NAK).
vasilito
945b87b7c1