intel: workaround infrastructure + regs_gt constants + initial tables
- regs_gt.rs: 100+ GT/engine register constants (offsets + field bits)
for Gen4-Gen12: L3 control, slice/row chicken, cache/sampler/WM
chicken, HSW, MCR, GAM/ECO, Gen11/Gen12, display WA registers
- workarounds.rs: uses regs_gt constants, 0 compilation errors
- mod.rs: wires regs_gt submodule
Tables present (initial, ~80 entries):
- GT: gen4, g4x, ilk, snb, ivb, hsw, gen8, gen9, icl, gen12
- Context: gen6, gen7, gen8, gen9, icl, gen12
- Engine: general_render_compute
- Whitelist: gen9, icl, gen12
Next: full exhaustive port of all remaining entries from
Linux 7.1 intel_workarounds.c (~400 more entries).
Red Bear
929eec0528