vasilito 58f8e8c6a7 intel: multi-generation power wells — Gen9 + Xe2 ...

Rewrite display_power.rs to support both Gen9 (Skylake) and Xe2
(Arrow Lake/Battlemage) power well initialization.

Gen9 path (unchanged): single POWER_WELL_CTL register at 0x45400
with bitmask for PW1/PW2/DDI_A-E/AUX_A-D domains.

Xe2 path (new): multiple power well controllers:
- HSW_PWR_WELL_CTL1 (0x45400) — PW1/PW2 per-index REQ/STATE
- ICL_PWR_WELL_CTL_AUX1 (0x45440) — 4 AUX channels
- ICL_PWR_WELL_CTL_DDI1 (0x45450) — 4 DDI ports
- DC_STATE_EN (0x45504) — DC power state control
Each well uses 2-bit per-index encoding (REQ=0x2, STATE=0x1).

DisplayPower::new() now takes &IntelDeviceInfo to select
generation-appropriate initialization path.

Linux reference: intel_display_power_well.c (xelpdp_aux_power_well_*)

2026-05-30 08:22:43 +03:00

..

base @ 12eb4be1c7

intel: multi-generation power wells — Gen9 + Xe2

2026-05-30 08:22:43 +03:00

bootloader @ b22a35c467

migrate: finalize source ownership — mini ISO builds and boots

2026-05-30 00:38:25 +03:00

installer @ 101a836a92

migrate: apply remaining patches to source forks, clean up

2026-05-29 22:48:03 +03:00

kernel @ 866dfad0af

migrate: restore fork repos from properly patched release archives

2026-05-29 23:07:54 +03:00

relibc @ 861bbb024a

migrate: restore fork repos from properly patched release archives

2026-05-29 23:07:54 +03:00