intel: DP link training — clock recovery + channel equalization
Add dp_link.rs implementing DisplayPort link training.
- train_dp_link(): reads DPCD caps, picks optimal link rate
(1.62/2.7/5.4 Gbps) and lane count (1/2/4), programs DDI,
runs clock recovery (pattern 1) and channel equalization
(pattern 2), then disables training pattern
- pick_link_rate(): selects highest supported link rate
- program_ddi(): configures DDI_BUF_CTL with port width
- clock_recovery(): polls DPCD LANE0_1_STATUS CR_DONE bits
- channel_equalization(): polls CHANNEL_EQ_DONE +
LANE_ALIGN_STATUS_UPDATED
- 100ms timeout, 5 retries per phase
Wire into IntelDriver constructor — train all DP links
for Xe2 platforms after DP AUX init, before display detection.
Linux reference: intel_dp_link_training.c
vasilito
7eb81aa1fe