vasilito
c0587f9a2d
The 556MB monolithic redox.patch was impossible to manage, unreviewable, blocked GitHub pushes, and could only grow. This commit: - Moves all 64 absorbed patches from absorbed/ to active use in base/ - Removes the absorbed/ directory (consolidation history is now PATCH-HISTORY.md) - Removes the redox.patch symlink from recipes/core/base/ - Fixes all recipe symlinks to point to active patches (not absorbed/) - Patches are now individually wired, reviewable, and independently rebasable The redox.patch mega-file is no longer needed — individual patches are applied directly from the recipe.toml patches list.
170 lines
7.8 KiB
Diff
170 lines
7.8 KiB
Diff
# P2-pcid-cfg-access.patch
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#
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# PCI config access error handling: replace unwrap()/expect()/assert!() with
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# proper error returns and graceful fallbacks in PCI configuration space access
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# (both I/O port fallback and ECAM/DTB paths).
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#
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# Covers:
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# - pcid/cfg_access/fallback.rs: I/O port rights error logging, offset overflow returns
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# - pcid/cfg_access/mod.rs: DTB property access with proper error propagation,
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# bus-range validation, interrupt-map phandle/property fallbacks
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#
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diff --git a/drivers/pcid/src/cfg_access/fallback.rs b/drivers/pcid/src/cfg_access/fallback.rs
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index 671d17f7..ea8f69f8 100644
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--- a/drivers/pcid/src/cfg_access/fallback.rs
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+++ b/drivers/pcid/src/cfg_access/fallback.rs
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@@ -33,7 +33,12 @@ impl Pci {
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"PCI: couldn't find or access PCIe extended configuration, \
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and thus falling back to PCI 3.0 io ports"
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);
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- common::acquire_port_io_rights().expect("pcid: failed to get IO port rights");
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+ common::acquire_port_io_rights()
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+ .map_err(|err| {
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+ log::error!("pcid: failed to get IO port rights: {err}");
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+ err
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+ })
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+ .expect("pcid: IO port rights required for PCI 3.0 fallback");
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}
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});
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}
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@@ -61,8 +66,9 @@ impl ConfigRegionAccess for Pci {
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Self::set_iopl();
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- let offset =
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- u8::try_from(offset).expect("offset too large for PCI 3.0 configuration space");
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+ let Ok(offset) = u8::try_from(offset) else {
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+ return 0xFFFFFFFF;
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+ };
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let address = Self::address(address, offset);
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Pio::<u32>::new(0xCF8).write(address);
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@@ -74,8 +80,9 @@ impl ConfigRegionAccess for Pci {
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Self::set_iopl();
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- let offset =
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- u8::try_from(offset).expect("offset too large for PCI 3.0 configuration space");
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+ let Ok(offset) = u8::try_from(offset) else {
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+ return;
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+ };
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let address = Self::address(address, offset);
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Pio::<u32>::new(0xCF8).write(address);
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diff --git a/drivers/pcid/src/cfg_access/mod.rs b/drivers/pcid/src/cfg_access/mod.rs
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index c2552448..0fe215a6 100644
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--- a/drivers/pcid/src/cfg_access/mod.rs
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+++ b/drivers/pcid/src/cfg_access/mod.rs
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@@ -38,42 +38,57 @@ fn locate_ecam_dtb<T>(
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)
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})?;
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- let address = node.reg().unwrap().next().unwrap().starting_address as u64;
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+ let mut reg = node.reg().ok_or_else(|| {
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+ io::Error::new(io::ErrorKind::NotFound, "pci-host-ecam-generic missing 'reg' property")
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+ })?;
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+ let address = reg.next().ok_or_else(|| {
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+ io::Error::new(io::ErrorKind::NotFound, "pci-host-ecam-generic 'reg' has no entries")
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+ })?.starting_address as u64;
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- let bus_range = node.property("bus-range").unwrap();
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- assert_eq!(bus_range.value.len(), 8);
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- let start_bus = u32::from_be_bytes(<[u8; 4]>::try_from(&bus_range.value[0..4]).unwrap());
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- let end_bus = u32::from_be_bytes(<[u8; 4]>::try_from(&bus_range.value[4..8]).unwrap());
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+ let bus_range = node.property("bus-range").ok_or_else(|| {
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+ io::Error::new(io::ErrorKind::NotFound, "pci-host-ecam-generic missing 'bus-range' property")
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+ })?;
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+ if bus_range.value.len() != 8 {
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+ return Err(io::Error::new(io::ErrorKind::InvalidData, "pci-host-ecam-generic 'bus-range' not 8 bytes"));
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+ }
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+ let start_bus = u32::from_be_bytes(<[u8; 4]>::try_from(&bus_range.value[0..4]).map_err(|_| io::Error::new(io::ErrorKind::InvalidData, "bus-range start parse failed"))?);
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+ let end_bus = u32::from_be_bytes(<[u8; 4]>::try_from(&bus_range.value[4..8]).map_err(|_| io::Error::new(io::ErrorKind::InvalidData, "bus-range end parse failed"))?);
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- // address-cells == 3, size-cells == 2, interrupt-cells == 1
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- let mut interrupt_map_data = node
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- .property("interrupt-map")
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- .unwrap()
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+ let interrupt_map_prop = node.property("interrupt-map").ok_or_else(|| {
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+ io::Error::new(io::ErrorKind::NotFound, "pci-host-ecam-generic missing 'interrupt-map' property")
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+ })?;
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+ let mut interrupt_map_data = interrupt_map_prop
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.value
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.chunks_exact(4)
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- .map(|x| u32::from_be_bytes(<[u8; 4]>::try_from(x).unwrap()));
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+ .map(|x| u32::from_be_bytes(<[u8; 4]>::try_from(x).unwrap_or([0, 0, 0, 0])));
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let mut interrupt_map = Vec::<InterruptMap>::new();
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while let Ok([addr1, addr2, addr3, int1, phandle]) = interrupt_map_data.next_chunk::<5>() {
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- let parent = dt.find_phandle(phandle).unwrap();
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- let parent_address_cells = u32::from_be_bytes(
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- parent.property("#address-cells").unwrap().value[..4]
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- .try_into()
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- .unwrap(),
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- );
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+ let Some(parent) = dt.find_phandle(phandle) else {
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+ log::warn!("pcid: DTB interrupt-map references phandle {phandle} not found, skipping");
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+ continue;
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+ };
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+ let parent_address_cells = match parent.property("#address-cells") {
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+ Some(prop) => u32::from_be_bytes(
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+ prop.value[..4]
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+ .try_into()
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+ .unwrap_or([0, 0, 0, 0]),
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+ ),
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+ None => 0,
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+ };
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match parent_address_cells {
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0 => {}
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1 => {
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- assert_eq!(interrupt_map_data.next().unwrap(), 0);
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+ let _ = interrupt_map_data.next();
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}
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2 => {
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- assert_eq!(interrupt_map_data.next_chunk::<2>().unwrap(), [0, 0]);
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+ let _ = interrupt_map_data.next_chunk::<2>();
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}
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3 => {
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- assert_eq!(interrupt_map_data.next_chunk::<3>().unwrap(), [0, 0, 0]);
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+ let _ = interrupt_map_data.next_chunk::<3>();
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}
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_ => break,
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};
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- let parent_interrupt_cells = parent.interrupt_cells().unwrap();
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+ let parent_interrupt_cells = parent.interrupt_cells().unwrap_or(1);
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let parent_interrupt = match parent_interrupt_cells {
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1 if let Some(a) = interrupt_map_data.next() => [a, 0, 0],
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2 if let Ok([a, b]) = interrupt_map_data.next_chunk::<2>() => [a, b, 0],
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@@ -94,8 +109,8 @@ fn locate_ecam_dtb<T>(
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let mut cells = interrupt_mask_node
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.value
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.chunks_exact(4)
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- .map(|x| u32::from_be_bytes(<[u8; 4]>::try_from(x).unwrap()));
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- cells.next_chunk::<4>().unwrap().to_owned()
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+ .map(|x| u32::from_be_bytes(<[u8; 4]>::try_from(x).unwrap_or([0, 0, 0, 0])));
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+ cells.next_chunk::<4>().unwrap_or([u32::MAX, u32::MAX, u32::MAX, u32::MAX]).to_owned()
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} else {
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[u32::MAX, u32::MAX, u32::MAX, u32::MAX]
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};
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@@ -104,8 +119,8 @@ fn locate_ecam_dtb<T>(
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PcieAllocs(&[PcieAlloc {
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base_addr: address,
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seg_group_num: 0,
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- start_bus: start_bus.try_into().unwrap(),
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- end_bus: end_bus.try_into().unwrap(),
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+ start_bus: start_bus.try_into().map_err(|_| io::Error::new(io::ErrorKind::InvalidData, "start_bus overflow"))?,
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+ end_bus: end_bus.try_into().map_err(|_| io::Error::new(io::ErrorKind::InvalidData, "end_bus overflow"))?,
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_rsvd: [0; 4],
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}]),
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interrupt_map,
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@@ -165,7 +180,10 @@ impl Mcfg {
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// crashing. `as_encoded_bytes()` returns some superset
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// of ASCII, so directly comparing it with an ASCII name
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// is fine.
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- let table_filename = table_path.file_name().unwrap().as_encoded_bytes();
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+ let table_filename = match table_path.file_name() {
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+ Some(name) => name.as_encoded_bytes(),
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+ None => continue,
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+ };
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if table_filename.get(0..4) == Some(&MCFG_NAME) {
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let bytes = fs::read(table_path)?.into_boxed_slice();
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match Mcfg::parse(&*bytes) {
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