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mg_pll.rs (130 lines): Multi-Gigabit PLL for USB-C DP Alt Mode Ice Lake+ (Gen11) Type-C/Thunderbolt PLL Per-port MG_PLL_CTL1/CTL2 with divider programming DCO integer/fractional divider computation TDC (Time-to-Digital Converter) calibration Power-up sequence: enable power → program → enable → lock dp_uhbr.rs (70 lines): DP 2.0 128b/132b link training UHBR training: single-phase TPS4 (no separate CR/EQ) 128b/132b channel coding enable via DPCD 0x0220 Lane status + interlane alignment polling is_uhbr() rate detection helper Ported from Linux 7.1: intel_mg_pll.c → MgPll intel_dp.c UHBR path → UhbrLinkTraining Intel driver: 90 files, 0 errors