vasilito
37738dc418
intel: replace remaining hardcoded register constants in mod.rs
Final cleanup of mod.rs — all display/GT register access now goes
through IntelRegs trait. Remaining hardcoded constants deleted.
Replacements:
- FORCEWAKE → regs.forcewake_req()
- PP_STATUS → self.regs.pp_status()
- PIPECONF_BASE → self.regs.pipeconf(0)
- PIPE_STRIDE → self.regs.pipe_stride()
- PIPEFRAME_REG → self.regs.pipeframe_reg(pipe)
- PIPEFRAME_COUNT_MASK → self.regs.pipeframe_count_mask()
- DDI_BUF_CTL_BASE → self.regs.ddi_buf_ctl(0)
- DDI_PORT_STRIDE → self.regs.ddi_port_stride()
- GFX_FLSH_CNTL_REG → self.regs.gfx_flsh_cntl()
Ring buffer constants (RENDER_RING_BASE, RING_TAIL_OFFSET,
RING_HEAD_OFFSET) kept — these are GPU engine registers
standardized by Intel across all generations, used in ring.rs
which doesn't need regs abstraction.
Compiled: 0 new errors (24 pre-existing in redox-driver-sys)
2026-05-30 07:52:58 +03:00
..
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