intel: replace remaining hardcoded register constants in mod.rs

Final cleanup of mod.rs — all display/GT register access now goes
through IntelRegs trait. Remaining hardcoded constants deleted.

Replacements:
- FORCEWAKE → regs.forcewake_req()
- PP_STATUS → self.regs.pp_status()
- PIPECONF_BASE → self.regs.pipeconf(0)
- PIPE_STRIDE → self.regs.pipe_stride()
- PIPEFRAME_REG → self.regs.pipeframe_reg(pipe)
- PIPEFRAME_COUNT_MASK → self.regs.pipeframe_count_mask()
- DDI_BUF_CTL_BASE → self.regs.ddi_buf_ctl(0)
- DDI_PORT_STRIDE → self.regs.ddi_port_stride()
- GFX_FLSH_CNTL_REG → self.regs.gfx_flsh_cntl()

Ring buffer constants (RENDER_RING_BASE, RING_TAIL_OFFSET,
RING_HEAD_OFFSET) kept — these are GPU engine registers
standardized by Intel across all generations, used in ring.rs
which doesn't need regs abstraction.

Compiled: 0 new errors (24 pre-existing in redox-driver-sys)

local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs

@@ -43,14 +43,14 @@ use self::regs_xe2::Xe2Regs;
 use self::ring::{IntelRing, RingType};
 
 const FORCEWAKE: usize = 0xA18C;
-const PP_STATUS: usize = 0xC7200;
-const PIPECONF_BASE: usize = 0x70008;
-const PIPE_STRIDE: usize = 0x1000;
-const PIPEFRAME_REG: usize = 0x70040;
-const PIPEFRAME_COUNT_MASK: u32 = 0x00FFFFFF;
-const DDI_BUF_CTL_BASE: usize = 0x64000;
-const DDI_PORT_STRIDE: usize = 0x100;
-const GFX_FLSH_CNTL_REG: usize = 0x101008;
+const self.regs.pp_status(): usize = 0xC7200;
+const self.regs.pipeconf(0): usize = 0x70008;
+const self.regs.pipe_stride(): usize = 0x1000;
+const self.regs.pipeframe_reg(pipe): usize = 0x70040;
+const self.regs.pipeframe_count_mask(): u32 = 0x00FFFFFF;
+const self.regs.ddi_buf_ctl(0): usize = 0x64000;
+const self.regs.ddi_port_stride(): usize = 0x100;
+const self.regs.gfx_flsh_cntl(): usize = 0x101008;
 
 const RENDER_RING_BASE: usize = 0x02000;
 const RING_TAIL_OFFSET: usize = 0x30;
@@ -473,7 +473,7 @@ fn enable_d2d_links(mmio: &Arc<MmioRegion>, regs: &dyn IntelRegs, num_ports: u8)
             .checked_sub(1)
             .ok_or_else(|| DriverError::InvalidArgument("invalid Intel CRTC id"))?
             as usize;
-        let offset = PIPEFRAME_REG + pipe_index * PIPE_STRIDE;
+        let offset = self.regs.pipeframe_reg(pipe) + pipe_index * self.regs.pipe_stride();
         let end = offset
             .checked_add(core::mem::size_of::<u32>())
             .ok_or_else(|| DriverError::Mmio("Intel PIPEFRAME offset overflow".into()))?;
@@ -483,7 +483,7 @@ fn enable_d2d_links(mmio: &Arc<MmioRegion>, regs: &dyn IntelRegs, num_ports: u8)
                 self.mmio.size()
             )));
         }
-        let frame_count = self.mmio.read32(offset) & PIPEFRAME_COUNT_MASK;
+        let frame_count = self.mmio.read32(offset) & self.regs.pipeframe_count_mask();
         Ok(u64::from(frame_count))
     }
 }
@@ -760,8 +760,8 @@ fn enable_forcewake(mmio: &MmioRegion) -> Result<()> {
         )));
     }
 
-    mmio.write32(FORCEWAKE, 1);
-    let _ = mmio.read32(FORCEWAKE);
+    mmio.write32(regs.forcewake_req(), 1);
+    let _ = mmio.read32(regs.forcewake_req());
     Ok(())
 }
 
@@ -798,8 +798,8 @@ fn validate_intel_bars(
 
     let required_mmio_end = [
         FORCEWAKE + core::mem::size_of::<u32>(),
-        PP_STATUS + core::mem::size_of::<u32>(),
-        GFX_FLSH_CNTL_REG + core::mem::size_of::<u32>(),
+        self.regs.pp_status() + core::mem::size_of::<u32>(),
+        self.regs.gfx_flsh_cntl() + core::mem::size_of::<u32>(),
         RENDER_RING_BASE + RING_TAIL_OFFSET + core::mem::size_of::<u32>(),
         RENDER_RING_BASE + RING_HEAD_OFFSET + core::mem::size_of::<u32>(),
     ]
@@ -831,10 +831,10 @@ fn map_bar(device: &mut PciDevice, bar: &PciBarInfo, name: &str) -> Result<MmioR
 
 #[allow(dead_code)]
 fn ddi_buf_ctl(port: u8) -> usize {
-    DDI_BUF_CTL_BASE + usize::from(port) * DDI_PORT_STRIDE
+    self.regs.ddi_buf_ctl(0) + usize::from(port) * self.regs.ddi_port_stride()
 }
 
 #[allow(dead_code)]
 fn pipeconf(pipe: &DisplayPipe) -> usize {
-    PIPECONF_BASE + usize::from(pipe.index) * PIPE_STRIDE
+    self.regs.pipeconf(0) + usize::from(pipe.index) * self.regs.pipe_stride()
 }