34360e1e4f
P0-P2: Barrier SMP, sigmask/pthread_kill races, robust mutexes, RT scheduling, POSIX sched API P3: PerCpuSched struct, per-CPU wiring, work stealing, load balancing, initial placement P4: 64-shard futex table, REQUEUE, PI futexes (LOCK_PI/UNLOCK_PI/TRYLOCK_PI), robust futexes, vruntime tracking, min-vruntime SCHED_OTHER selection P5: setpriority/getpriority, pthread_setaffinity_np, pthread_setname_np, pthread_setschedparam (Redox) P6: Cache-affine scheduling (last_cpu + vruntime bonus), NUMA topology kernel hints + numad userspace daemon Stability fixes: make_consistent stores 0 (dead TID fix), cond.rs error propagation, SPIN_COUNT adaptive spinning, Sys::open &str fix, PI futex CAS race, proc.rs lock ordering, barrier destroy Patches: 33 kernel + 58 relibc patches, all tracked in recipes Docs: KERNEL-SCHEDULER-MULTITHREAD-IMPROVEMENT-PLAN.md updated, SCHEDULER-REVIEW-FINAL.md created Architecture: NUMA topology parsing stays userspace (numad daemon), kernel stores lightweight NumaTopology hints
183 lines
7.5 KiB
Diff
183 lines
7.5 KiB
Diff
diff --git a/drivers/pcid/src/scheme.rs b/drivers/pcid/src/scheme.rs
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index bb9f39a3..06be6267 100644
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--- a/drivers/pcid/src/scheme.rs
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+++ b/drivers/pcid/src/scheme.rs
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@@ -1,11 +1,11 @@
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-use std::collections::{BTreeMap, VecDeque};
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+use std::collections::{BTreeMap, HashMap, VecDeque};
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use pci_types::{ConfigRegionAccess, PciAddress};
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use redox_scheme::scheme::SchemeSync;
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use redox_scheme::{CallerCtx, OpenResult};
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use scheme_utils::HandleMap;
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use syscall::dirent::{DirEntry, DirentBuf, DirentKind};
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-use syscall::error::{Error, Result, EACCES, EBADF, EINVAL, EIO, EISDIR, ENOENT, ENOTDIR};
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+use syscall::error::{Error, Result, EACCES, EBADF, EINVAL, EIO, EISDIR, ENOENT, ENOTDIR, EALREADY};
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use syscall::flag::{MODE_CHR, MODE_DIR, O_DIRECTORY, O_STAT};
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use syscall::schemev2::NewFdFlags;
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use syscall::ENOLCK;
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@@ -16,6 +16,8 @@ pub struct PciScheme {
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handles: HandleMap<HandleWrapper>,
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pub pcie: Pcie,
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pub tree: BTreeMap<PciAddress, crate::Func>,
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+ /// Maps device address string (e.g. "0000:00:14.0") to owning PID
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+ binds: HashMap<String, u32>,
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}
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enum Handle {
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TopLevel { entries: Vec<String> },
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@@ -23,6 +25,12 @@ enum Handle {
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Device,
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Channel { addr: PciAddress, st: ChannelState },
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SchemeRoot,
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+ /// Represents an open handle to a device's bind endpoint
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+ Bind { addr: PciAddress },
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+ /// Uevent surface for hotplug consumers. Opening uevent returns an object
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+ /// from which device add/remove events can be read. Since pcid currently
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+ /// only scans at startup, this surface is ready for hotplug polling consumers.
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+ Uevent,
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}
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struct HandleWrapper {
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inner: Handle,
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@@ -30,14 +38,13 @@ struct HandleWrapper {
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}
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impl Handle {
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fn is_file(&self) -> bool {
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- matches!(self, Self::Access | Self::Channel { .. })
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+ matches!(self, Self::Access | Self::Channel { .. } | Self::Bind { .. } | Self::Uevent)
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}
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fn is_dir(&self) -> bool {
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!self.is_file()
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}
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- // TODO: capability rather than root
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fn requires_root(&self) -> bool {
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- matches!(self, Self::Access | Self::Channel { .. })
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+ matches!(self, Self::Access | Self::Channel { .. } | Self::Bind { .. })
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}
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fn is_scheme_root(&self) -> bool {
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matches!(self, Self::SchemeRoot)
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@@ -49,7 +56,7 @@ enum ChannelState {
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AwaitingResponseRead(VecDeque<u8>),
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}
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-const DEVICE_CONTENTS: &[&str] = &["channel"];
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+const DEVICE_CONTENTS: &[&str] = &["channel", "bind"];
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impl PciScheme {
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pub fn access(&mut self) -> usize {
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@@ -88,22 +95,25 @@ impl SchemeSync for PciScheme {
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let path = path.trim_matches('/');
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let handle = if path.is_empty() {
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- Handle::TopLevel {
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- entries: self
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- .tree
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- .iter()
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- // FIXME remove replacement of : once the old scheme format is no longer supported.
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- .map(|(addr, _)| format!("{}", addr).replace(':', "--"))
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- .collect::<Vec<_>>(),
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- }
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+ let mut entries: Vec<String> = self
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+ .tree
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+ .iter()
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+ // FIXME remove replacement of : once the old scheme format is no longer supported.
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+ .map(|(addr, _)| format!("{}", addr).replace(':', "--"))
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+ .collect();
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+ entries.push(String::from("uevent"));
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+ entries.push(String::from("access"));
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+ Handle::TopLevel { entries }
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} else if path == "access" {
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Handle::Access
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+ } else if path == "uevent" {
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+ Handle::Uevent
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} else {
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let idx = path.find('/').unwrap_or(path.len());
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let (addr_str, after) = path.split_at(idx);
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let addr = parse_pci_addr(addr_str).ok_or(Error::new(ENOENT))?;
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- self.parse_after_pci_addr(addr, after)?
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+ self.parse_after_pci_addr(addr, after, ctx)?
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};
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let stat = flags & O_STAT != 0;
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@@ -132,7 +142,8 @@ impl SchemeSync for PciScheme {
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let (len, mode) = match handle.inner {
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Handle::TopLevel { ref entries } => (entries.len(), MODE_DIR | 0o755),
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Handle::Device => (DEVICE_CONTENTS.len(), MODE_DIR | 0o755),
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- Handle::Access | Handle::Channel { .. } => (0, MODE_CHR | 0o600),
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+ Handle::Access | Handle::Channel { .. } | Handle::Bind { .. } => (0, MODE_CHR | 0o600),
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+ Handle::Uevent => (0, MODE_CHR | 0o644),
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Handle::SchemeRoot => return Err(Error::new(EBADF)),
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};
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stat.st_size = len as u64;
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@@ -160,7 +171,13 @@ impl SchemeSync for PciScheme {
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addr: _,
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ref mut st,
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} => Self::read_channel(st, buf),
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- Handle::SchemeRoot => Err(Error::new(EBADF)),
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+ Handle::Uevent => {
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+ // Uevent surface is ready for hotplug polling consumers.
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+ // pcid currently only scans at startup, so return empty (EAGAIN would indicate no data available).
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+ // Consumers can poll and re-read to check for new events.
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+ Ok(0)
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+ }
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+ Handle::SchemeRoot | Handle::Bind { .. } => Err(Error::new(EBADF)),
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_ => Err(Error::new(EBADF)),
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}
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}
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@@ -193,7 +210,7 @@ impl SchemeSync for PciScheme {
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return Ok(buf);
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}
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Handle::Device => DEVICE_CONTENTS,
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- Handle::Access | Handle::Channel { .. } => return Err(Error::new(ENOTDIR)),
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+ Handle::Access | Handle::Channel { .. } | Handle::Bind { .. } | Handle::Uevent => return Err(Error::new(ENOTDIR)),
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Handle::SchemeRoot => return Err(Error::new(EBADF)),
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};
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@@ -316,6 +333,16 @@ impl SchemeSync for PciScheme {
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func.enabled = false;
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}
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}
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+ Some(HandleWrapper {
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+ inner: Handle::Bind { addr },
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+ ..
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+ }) => {
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+ let addr_str = format!("{}", addr);
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+ if let Some(&owner_pid) = self.binds.get(&addr_str) {
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+ log::info!("pcid: device {} unbound by pid {}", addr_str, owner_pid);
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+ }
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+ self.binds.remove(&addr_str);
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+ }
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_ => {}
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}
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}
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@@ -327,9 +354,10 @@ impl PciScheme {
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handles: HandleMap::new(),
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pcie,
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tree: BTreeMap::new(),
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+ binds: HashMap::new(),
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}
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}
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- fn parse_after_pci_addr(&mut self, addr: PciAddress, after: &str) -> Result<Handle> {
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+ fn parse_after_pci_addr(&mut self, addr: PciAddress, after: &str, ctx: &CallerCtx) -> Result<Handle> {
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if after.chars().next().map_or(false, |c| c != '/') {
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return Err(Error::new(ENOENT));
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}
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@@ -356,6 +384,17 @@ impl PciScheme {
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st: ChannelState::AwaitingData,
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}
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}
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+ "bind" => {
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+ let addr_str = format!("{}", addr);
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+ if let Some(&owner_pid) = self.binds.get(&addr_str) {
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+ log::info!("pcid: device {} already bound by pid {}", addr_str, owner_pid);
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+ return Err(Error::new(EALREADY));
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+ }
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+ let caller_pid = ctx.pid;
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+ self.binds.insert(addr_str.clone(), caller_pid);
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+ log::info!("pcid: device {} bound by pid {}", addr_str, caller_pid);
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+ Handle::Bind { addr }
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+ }
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_ => return Err(Error::new(ENOENT)),
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}
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})
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