vasilito
7686729069
Extract protocol-agnostic FenceTimeline from Intel to shared src/drivers/fence.rs — atomic-based fence tracking suitable for Intel, VIRGL, and AMD drivers. Extract protocol-agnostic SyncobjManager from Intel to shared src/drivers/syncobj.rs — syncobj create/destroy/signal/reset/ wait/query and sync_file fd export/import. Wire both into VirtioDriver: - Add FenceTimeline + SyncobjManager fields - Implement all 5 GpuDriver syncobj trait methods (create, destroy, wait, export_fd, import_fd) - Track fence seqnos in virgl_submit_3d (allocate before submit, signal after completion) Intel fence.rs and syncobj.rs converted to thin re-export modules pointing at shared sources — no behavioral change for Intel driver. This gives Mesa VIRGL userspace the standard DRM syncobj API for GPU/compositor synchronization.
33 lines
983 B
Python
33 lines
983 B
Python
# coding: utf-8
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import unittest
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import magic
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class MagicTestCase(unittest.TestCase):
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filename = 'magic.py'
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expected_mime_type = 'text/x-script.python'
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expected_encoding = 'us-ascii'
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expected_name = 'Python script, ASCII text executable'
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def assert_result(self, result):
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self.assertEqual(result.mime_type, self.expected_mime_type)
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self.assertEqual(result.encoding, self.expected_encoding)
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self.assertEqual(result.name, self.expected_name)
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def test_detect_from_filename(self):
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result = magic.detect_from_filename(self.filename)
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self.assert_result(result)
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def test_detect_from_fobj(self):
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with open(self.filename, "rb") as fobj:
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result = magic.detect_from_fobj(fobj)
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self.assert_result(result)
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def test_detect_from_content(self):
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with open(self.filename, "rb") as fobj:
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result = magic.detect_from_content(fobj.read(8192))
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self.assert_result(result)
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