Red Bear OS
334 lines
9.3 KiB
Rust
334 lines
9.3 KiB
Rust
use common::io::Pio;
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use redox_scheme::scheme::SchemeSync;
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use redox_scheme::CallerCtx;
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use redox_scheme::OpenResult;
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use scheme_utils::{FpathWriter, HandleMap};
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use syscall::error::{Error, Result, EACCES, EBADF, EINVAL, ENOENT};
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use syscall::schemev2::NewFdFlags;
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use syscall::EWOULDBLOCK;
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use common::{
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dma::Dma,
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io::{Io, Mmio},
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};
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use spin::Mutex;
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const NUM_SUB_BUFFS: usize = 32;
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const SUB_BUFF_SIZE: usize = 2048;
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enum Handle {
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Todo,
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SchemeRoot,
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}
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#[allow(dead_code)]
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struct MixerRegs {
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/* 0x00 */ reset: Pio<u16>,
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/* 0x02 */ master_volume: Pio<u16>,
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/* 0x04 */ aux_out_volume: Pio<u16>,
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/* 0x06 */ mono_volume: Pio<u16>,
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/* 0x08 */ master_tone: Pio<u16>,
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/* 0x0A */ pc_beep_volume: Pio<u16>,
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/* 0x0C */ phone_volume: Pio<u16>,
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/* 0x0E */ mic_volume: Pio<u16>,
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/* 0x10 */ line_in_volume: Pio<u16>,
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/* 0x12 */ cd_volume: Pio<u16>,
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/* 0x14 */ video_volume: Pio<u16>,
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/* 0x16 */ aux_in_volume: Pio<u16>,
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/* 0x18 */ pcm_out_volume: Pio<u16>,
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/* 0x1A */ record_select: Pio<u16>,
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/* 0x1C */ record_gain: Pio<u16>,
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/* 0x1E */ record_gain_mic: Pio<u16>,
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/* 0x20 */ general_purpose: Pio<u16>,
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/* 0x22 */ control_3d: Pio<u16>,
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/* 0x24 */ audio_int_paging: Pio<u16>,
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/* 0x26 */ powerdown: Pio<u16>,
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/* 0x28 */ extended_id: Pio<u16>,
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/* 0x2A */ extended_ctrl: Pio<u16>,
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/* 0x2C */ vra_pcm_front: Pio<u16>,
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}
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impl MixerRegs {
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fn new(bar0: u16) -> Self {
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Self {
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reset: Pio::new(bar0 + 0x00),
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master_volume: Pio::new(bar0 + 0x02),
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aux_out_volume: Pio::new(bar0 + 0x04),
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mono_volume: Pio::new(bar0 + 0x06),
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master_tone: Pio::new(bar0 + 0x08),
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pc_beep_volume: Pio::new(bar0 + 0x0A),
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phone_volume: Pio::new(bar0 + 0x0C),
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mic_volume: Pio::new(bar0 + 0x0E),
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line_in_volume: Pio::new(bar0 + 0x10),
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cd_volume: Pio::new(bar0 + 0x12),
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video_volume: Pio::new(bar0 + 0x14),
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aux_in_volume: Pio::new(bar0 + 0x16),
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pcm_out_volume: Pio::new(bar0 + 0x18),
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record_select: Pio::new(bar0 + 0x1A),
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record_gain: Pio::new(bar0 + 0x1C),
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record_gain_mic: Pio::new(bar0 + 0x1E),
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general_purpose: Pio::new(bar0 + 0x20),
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control_3d: Pio::new(bar0 + 0x22),
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audio_int_paging: Pio::new(bar0 + 0x24),
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powerdown: Pio::new(bar0 + 0x26),
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extended_id: Pio::new(bar0 + 0x28),
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extended_ctrl: Pio::new(bar0 + 0x2A),
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vra_pcm_front: Pio::new(bar0 + 0x2C),
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}
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}
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}
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#[allow(dead_code)]
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struct BusBoxRegs {
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/// Buffer descriptor list base address
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/* 0x00 */
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bdbar: Pio<u32>,
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/// Current index value
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/* 0x04 */
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civ: Pio<u8>,
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/// Last valid index
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/* 0x05 */
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lvi: Pio<u8>,
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/// Status
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/* 0x06 */
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sr: Pio<u16>,
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/// Position in current buffer
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/* 0x08 */
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picb: Pio<u16>,
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/// Prefetched index value
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/* 0x0A */
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piv: Pio<u8>,
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/// Control
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/* 0x0B */
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cr: Pio<u8>,
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}
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impl BusBoxRegs {
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fn new(base: u16) -> Self {
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Self {
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bdbar: Pio::new(base + 0x00),
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civ: Pio::new(base + 0x04),
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lvi: Pio::new(base + 0x05),
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sr: Pio::new(base + 0x06),
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picb: Pio::new(base + 0x08),
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piv: Pio::new(base + 0x0A),
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cr: Pio::new(base + 0x0B),
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}
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}
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}
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#[allow(dead_code)]
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struct BusRegs {
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/// PCM in register box
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/* 0x00 */
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pi: BusBoxRegs,
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/// PCM out register box
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/* 0x10 */
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po: BusBoxRegs,
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/// Microphone register box
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/* 0x20 */
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mc: BusBoxRegs,
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}
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impl BusRegs {
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fn new(bar1: u16) -> Self {
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Self {
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pi: BusBoxRegs::new(bar1 + 0x00),
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po: BusBoxRegs::new(bar1 + 0x10),
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mc: BusBoxRegs::new(bar1 + 0x20),
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}
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}
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}
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#[repr(C, packed)]
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pub struct BufferDescriptor {
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/* 0x00 */ addr: Mmio<u32>,
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/* 0x04 */ samples: Mmio<u16>,
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/* 0x06 */ flags: Mmio<u16>,
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}
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pub struct Ac97 {
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mixer: MixerRegs,
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bus: BusRegs,
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bdl: Dma<[BufferDescriptor; NUM_SUB_BUFFS]>,
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buf: Dma<[u8; NUM_SUB_BUFFS * SUB_BUFF_SIZE]>,
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handles: Mutex<HandleMap<Handle>>,
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}
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impl Ac97 {
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pub unsafe fn new(bar0: u16, bar1: u16) -> Result<Self> {
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let mut module = Ac97 {
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mixer: MixerRegs::new(bar0),
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bus: BusRegs::new(bar1),
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bdl: Dma::zeroed(
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//TODO: PhysBox::new_in_32bit_space(bdl_size)?
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)?
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.assume_init(),
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buf: Dma::zeroed(
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//TODO: PhysBox::new_in_32bit_space(buf_size)?
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)?
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.assume_init(),
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handles: Mutex::new(HandleMap::new()),
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};
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module.init()?;
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Ok(module)
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}
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fn init(&mut self) -> Result<()> {
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//TODO: support other sample rates, or just the default of 48000 Hz
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{
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// Check if VRA is supported
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if !self.mixer.extended_id.readf(1 << 0) {
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println!("ac97d: VRA not supported and is currently required");
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return Err(Error::new(ENOENT));
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}
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// Enable VRA
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self.mixer.extended_ctrl.writef(1 << 0, true);
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// Attempt to set sample rate for PCM front to 44100 Hz
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let desired_sample_rate = 44100;
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self.mixer.vra_pcm_front.write(desired_sample_rate);
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// Read back real sample rate
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let real_sample_rate = self.mixer.vra_pcm_front.read();
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println!("ac97d: set sample rate to {}", real_sample_rate);
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// Error if we cannot set the sample rate as desired
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if real_sample_rate != desired_sample_rate {
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println!(
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"ac97d: sample rate is {} but only {} is supported",
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real_sample_rate, desired_sample_rate
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);
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return Err(Error::new(ENOENT));
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}
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}
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// Ensure PCM out is stopped
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self.bus.po.cr.writef(1, false);
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// Reset PCM out
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self.bus.po.cr.writef(1 << 1, true);
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while self.bus.po.cr.readf(1 << 1) {
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// Spinning on resetting PCM out
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//TODO: relax
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}
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// Initialize BDL for PCM out
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for i in 0..NUM_SUB_BUFFS {
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self.bdl[i]
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.addr
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.write((self.buf.physical() + i * SUB_BUFF_SIZE) as u32);
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self.bdl[i]
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.samples
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.write((SUB_BUFF_SIZE / 2/* Each sample is i16 or 2 bytes */) as u16);
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self.bdl[i]
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.flags
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.write(1 << 15 /* Interrupt on completion */);
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}
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self.bus.po.bdbar.write(self.bdl.physical() as u32);
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// Enable interrupt on completion
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self.bus.po.cr.writef(1 << 4, true);
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// Start bus master
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self.bus.po.cr.writef(1 << 0, true);
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// Set master volume to 0 db (loudest output, DANGER!)
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self.mixer.master_volume.write(0);
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// Set PCM output volume to 0 db (medium)
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self.mixer.pcm_out_volume.write(0x808);
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Ok(())
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}
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pub fn irq(&mut self) -> bool {
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let ints = self.bus.po.sr.read() & 0b11100;
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if ints != 0 {
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self.bus.po.sr.write(ints);
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true
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} else {
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false
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}
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}
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}
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impl SchemeSync for Ac97 {
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fn scheme_root(&mut self) -> Result<usize> {
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Ok(self.handles.lock().insert(Handle::SchemeRoot))
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}
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fn openat(
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&mut self,
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dirfd: usize,
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_path: &str,
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_flags: usize,
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_fcntl_flags: u32,
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ctx: &CallerCtx,
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) -> Result<OpenResult> {
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{
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let handles = self.handles.lock();
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let handle = handles.get(dirfd)?;
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if !matches!(handle, Handle::SchemeRoot) {
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return Err(Error::new(EACCES));
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}
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}
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if ctx.uid == 0 {
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let id = self.handles.lock().insert(Handle::Todo);
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Ok(OpenResult::ThisScheme {
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number: id,
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flags: NewFdFlags::empty(),
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})
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} else {
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Err(Error::new(EACCES))
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}
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}
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fn write(
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&mut self,
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id: usize,
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buf: &[u8],
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_offset: u64,
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_flags: u32,
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_ctx: &CallerCtx,
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) -> Result<usize> {
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{
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let mut handles = self.handles.lock();
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let handle = handles.get_mut(id)?;
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if !matches!(handle, Handle::Todo) {
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return Err(Error::new(EBADF));
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}
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}
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if buf.len() != SUB_BUFF_SIZE {
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return Err(Error::new(EINVAL));
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}
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let civ = self.bus.po.civ.read() as usize;
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let mut lvi = self.bus.po.lvi.read() as usize;
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if lvi == (civ + 3) % NUM_SUB_BUFFS {
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// Block if we already are 3 buffers ahead
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Err(Error::new(EWOULDBLOCK))
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} else {
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// Fill next buffer
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lvi = (lvi + 1) % NUM_SUB_BUFFS;
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for i in 0..SUB_BUFF_SIZE {
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self.buf[lvi * SUB_BUFF_SIZE + i] = buf[i];
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}
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self.bus.po.lvi.write(lvi as u8);
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Ok(SUB_BUFF_SIZE)
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}
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}
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fn fpath(&mut self, _id: usize, buf: &mut [u8], _ctx: &CallerCtx) -> Result<usize> {
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FpathWriter::with(buf, "audiohw", |_| Ok(()))
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}
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fn on_close(&mut self, id: usize) {
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self.handles.lock().remove(id);
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}
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}
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