drm: implement AMD private CS submit/wait via SDMA ring buffer
- Add RingManager::submit_batch() — submits dwords with auto-fence
- Add RingManager::last_seqno() — returns latest sequence number
- Add RingManager::sync_from_hw() — reads hardware-completed seqno from fence buffer
- Add RingManager::flush() — memory fence + hardware sync
- Wire AmdDriver::redox_private_cs_submit — reads batch from GEM,
submits to SDMA ring with flush, returns fence seqno
- Wire AmdDriver::redox_private_cs_wait — polls SDMA fence seqno
with configurable timeout, uses ring.sync_from_hw() for hardware
completion tracking
Replaces the Unsupported stub. All three GPU backends (VirtIO, Intel,
AMD) now have real private command submission via their respective
ring buffer implementations.
vasilito
b579eda0c6