build: cleanup script to free 58GB of build artifacts
- Remove recipe target directories (47GB) - Clean build directory artifacts - Remove old temp logs - Clean Cargo target directories - Free disk space from 32GB to 91GB available
This commit is contained in:
@@ -1,571 +0,0 @@
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//! Core task module.
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//!
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//! # Safety
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//!
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//! The functions in this module are private to the `task` module. All of them
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//! should be considered `unsafe` to use, but are not marked as such since it
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//! would be too noisy.
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//!
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//! Make sure to consult the relevant safety section of each function before
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//! use.
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// It doesn't make sense to enforce `unsafe_op_in_unsafe_fn` for this module because
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//
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// * This module is doing the low-level task management that requires tons of unsafe
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// operations.
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// * Excessive `unsafe {}` blocks hurt readability significantly.
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// TODO: replace with `#[expect(unsafe_op_in_unsafe_fn)]` after bumpping
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// the MSRV to 1.81.0.
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#![allow(unsafe_op_in_unsafe_fn)]
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use crate::future::Future;
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use crate::loom::cell::UnsafeCell;
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use crate::runtime::context;
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use crate::runtime::task::raw::{self, Vtable};
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use crate::runtime::task::state::State;
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use crate::runtime::task::{Id, Schedule, TaskHarnessScheduleHooks};
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use crate::util::linked_list;
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use std::num::NonZeroU64;
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#[cfg(tokio_unstable)]
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use std::panic::Location;
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use std::pin::Pin;
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use std::ptr::NonNull;
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use std::task::{Context, Poll, Waker};
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/// The task cell. Contains the components of the task.
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///
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/// It is critical for `Header` to be the first field as the task structure will
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/// be referenced by both *mut Cell and *mut Header.
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///
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/// Any changes to the layout of this struct _must_ also be reflected in the
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/// `const` fns in raw.rs.
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///
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// # This struct should be cache padded to avoid false sharing. The cache padding rules are copied
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// from crossbeam-utils/src/cache_padded.rs
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//
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// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache
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// lines at a time, so we have to align to 128 bytes rather than 64.
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//
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// Sources:
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// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
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// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
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//
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// ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
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//
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// Sources:
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// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
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//
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// powerpc64 has 128-byte cache line size.
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//
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// Sources:
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
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#[cfg_attr(
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any(
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target_arch = "x86_64",
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target_arch = "aarch64",
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target_arch = "powerpc64",
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),
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repr(align(128))
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)]
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// arm, mips, mips64, sparc, and hexagon have 32-byte cache line size.
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//
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// Sources:
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
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// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L17
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// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/hexagon/include/asm/cache.h#L12
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#[cfg_attr(
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any(
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target_arch = "arm",
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target_arch = "mips",
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target_arch = "mips64",
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target_arch = "sparc",
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target_arch = "hexagon",
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),
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repr(align(32))
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)]
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// m68k has 16-byte cache line size.
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//
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// Sources:
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// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/m68k/include/asm/cache.h#L9
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#[cfg_attr(target_arch = "m68k", repr(align(16)))]
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// s390x has 256-byte cache line size.
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//
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// Sources:
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
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// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/s390/include/asm/cache.h#L13
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#[cfg_attr(target_arch = "s390x", repr(align(256)))]
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// x86, riscv, wasm, and sparc64 have 64-byte cache line size.
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//
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// Sources:
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// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
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// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L19
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// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/riscv/include/asm/cache.h#L10
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//
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// All others are assumed to have 64-byte cache line size.
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#[cfg_attr(
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not(any(
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target_arch = "x86_64",
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target_arch = "aarch64",
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target_arch = "powerpc64",
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target_arch = "arm",
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target_arch = "mips",
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target_arch = "mips64",
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target_arch = "sparc",
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target_arch = "hexagon",
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target_arch = "m68k",
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target_arch = "s390x",
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)),
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repr(align(64))
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)]
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#[repr(C)]
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pub(super) struct Cell<T: Future, S> {
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/// Hot task state data
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pub(super) header: Header,
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/// Either the future or output, depending on the execution stage.
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pub(super) core: Core<T, S>,
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/// Cold data
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pub(super) trailer: Trailer,
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}
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pub(super) struct CoreStage<T: Future> {
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stage: UnsafeCell<Stage<T>>,
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}
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/// The core of the task.
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///
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/// Holds the future or output, depending on the stage of execution.
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///
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/// Any changes to the layout of this struct _must_ also be reflected in the
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/// `const` fns in raw.rs.
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#[repr(C)]
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pub(super) struct Core<T: Future, S> {
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/// Scheduler used to drive this future.
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pub(super) scheduler: S,
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/// The task's ID, used for populating `JoinError`s.
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pub(super) task_id: Id,
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/// The source code location where the task was spawned.
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///
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/// This is used for populating the `TaskMeta` passed to the task runtime
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/// hooks.
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#[cfg(tokio_unstable)]
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pub(super) spawned_at: &'static Location<'static>,
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/// Either the future or the output.
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pub(super) stage: CoreStage<T>,
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}
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/// Crate public as this is also needed by the pool.
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#[repr(C)]
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pub(crate) struct Header {
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/// Task state.
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pub(super) state: State,
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/// Pointer to next task, used with the injection queue.
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pub(super) queue_next: UnsafeCell<Option<NonNull<Header>>>,
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/// Table of function pointers for executing actions on the task.
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pub(super) vtable: &'static Vtable,
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/// This integer contains the id of the `OwnedTasks` or `LocalOwnedTasks`
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/// that this task is stored in. If the task is not in any list, should be
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/// the id of the list that it was previously in, or `None` if it has never
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/// been in any list.
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///
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/// Once a task has been bound to a list, it can never be bound to another
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/// list, even if removed from the first list.
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///
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/// The id is not unset when removed from a list because we want to be able
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/// to read the id without synchronization, even if it is concurrently being
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/// removed from the list.
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pub(super) owner_id: UnsafeCell<Option<NonZeroU64>>,
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/// The tracing ID for this instrumented task.
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#[cfg(all(tokio_unstable, feature = "tracing"))]
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pub(super) tracing_id: Option<tracing::Id>,
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}
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unsafe impl Send for Header {}
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unsafe impl Sync for Header {}
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/// Cold data is stored after the future. Data is considered cold if it is only
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/// used during creation or shutdown of the task.
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pub(super) struct Trailer {
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/// Pointers for the linked list in the `OwnedTasks` that owns this task.
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pub(super) owned: linked_list::Pointers<Header>,
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/// Consumer task waiting on completion of this task.
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pub(super) waker: UnsafeCell<Option<Waker>>,
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/// Optional hooks needed in the harness.
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#[cfg_attr(not(tokio_unstable), allow(dead_code))] //TODO: remove when hooks are stabilized
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pub(super) hooks: TaskHarnessScheduleHooks,
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}
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generate_addr_of_methods! {
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impl<> Trailer {
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pub(super) unsafe fn addr_of_owned(self: NonNull<Self>) -> NonNull<linked_list::Pointers<Header>> {
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&self.owned
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}
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}
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}
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|
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/// Either the future or the output.
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#[repr(C)] // https://github.com/rust-lang/miri/issues/3780
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pub(super) enum Stage<T: Future> {
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Running(T),
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Finished(super::Result<T::Output>),
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Consumed,
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}
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impl<T: Future, S: Schedule> Cell<T, S> {
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/// Allocates a new task cell, containing the header, trailer, and core
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/// structures.
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pub(super) fn new(
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future: T,
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scheduler: S,
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state: State,
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task_id: Id,
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#[cfg(tokio_unstable)] spawned_at: &'static Location<'static>,
|
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) -> Box<Cell<T, S>> {
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// Separated into a non-generic function to reduce LLVM codegen
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fn new_header(
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state: State,
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vtable: &'static Vtable,
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#[cfg(all(tokio_unstable, feature = "tracing"))] tracing_id: Option<tracing::Id>,
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) -> Header {
|
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Header {
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state,
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queue_next: UnsafeCell::new(None),
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vtable,
|
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owner_id: UnsafeCell::new(None),
|
||||
#[cfg(all(tokio_unstable, feature = "tracing"))]
|
||||
tracing_id,
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(all(tokio_unstable, feature = "tracing"))]
|
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let tracing_id = future.id();
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||||
let vtable = raw::vtable::<T, S>();
|
||||
let result = Box::new(Cell {
|
||||
trailer: Trailer::new(scheduler.hooks()),
|
||||
header: new_header(
|
||||
state,
|
||||
vtable,
|
||||
#[cfg(all(tokio_unstable, feature = "tracing"))]
|
||||
tracing_id,
|
||||
),
|
||||
core: Core {
|
||||
scheduler,
|
||||
stage: CoreStage {
|
||||
stage: UnsafeCell::new(Stage::Running(future)),
|
||||
},
|
||||
task_id,
|
||||
#[cfg(tokio_unstable)]
|
||||
spawned_at,
|
||||
},
|
||||
});
|
||||
|
||||
#[cfg(debug_assertions)]
|
||||
{
|
||||
// Using a separate function for this code avoids instantiating it separately for every `T`.
|
||||
unsafe fn check<S>(
|
||||
header: &Header,
|
||||
trailer: &Trailer,
|
||||
scheduler: &S,
|
||||
task_id: &Id,
|
||||
#[cfg(tokio_unstable)] spawn_location: &&'static Location<'static>,
|
||||
) {
|
||||
let trailer_addr = trailer as *const Trailer as usize;
|
||||
let trailer_ptr = unsafe { Header::get_trailer(NonNull::from(header)) };
|
||||
assert_eq!(trailer_addr, trailer_ptr.as_ptr() as usize);
|
||||
|
||||
let scheduler_addr = scheduler as *const S as usize;
|
||||
let scheduler_ptr = unsafe { Header::get_scheduler::<S>(NonNull::from(header)) };
|
||||
assert_eq!(scheduler_addr, scheduler_ptr.as_ptr() as usize);
|
||||
|
||||
let id_addr = task_id as *const Id as usize;
|
||||
let id_ptr = unsafe { Header::get_id_ptr(NonNull::from(header)) };
|
||||
assert_eq!(id_addr, id_ptr.as_ptr() as usize);
|
||||
|
||||
#[cfg(tokio_unstable)]
|
||||
{
|
||||
let spawn_location_addr =
|
||||
spawn_location as *const &'static Location<'static> as usize;
|
||||
let spawn_location_ptr =
|
||||
unsafe { Header::get_spawn_location_ptr(NonNull::from(header)) };
|
||||
assert_eq!(spawn_location_addr, spawn_location_ptr.as_ptr() as usize);
|
||||
}
|
||||
}
|
||||
unsafe {
|
||||
check(
|
||||
&result.header,
|
||||
&result.trailer,
|
||||
&result.core.scheduler,
|
||||
&result.core.task_id,
|
||||
#[cfg(tokio_unstable)]
|
||||
&result.core.spawned_at,
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
result
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Future> CoreStage<T> {
|
||||
pub(super) fn with_mut<R>(&self, f: impl FnOnce(*mut Stage<T>) -> R) -> R {
|
||||
self.stage.with_mut(f)
|
||||
}
|
||||
}
|
||||
|
||||
/// Set and clear the task id in the context when the future is executed or
|
||||
/// dropped, or when the output produced by the future is dropped.
|
||||
pub(crate) struct TaskIdGuard {
|
||||
parent_task_id: Option<Id>,
|
||||
}
|
||||
|
||||
impl TaskIdGuard {
|
||||
fn enter(id: Id) -> Self {
|
||||
TaskIdGuard {
|
||||
parent_task_id: context::set_current_task_id(Some(id)),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Drop for TaskIdGuard {
|
||||
fn drop(&mut self) {
|
||||
context::set_current_task_id(self.parent_task_id);
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Future, S: Schedule> Core<T, S> {
|
||||
/// Polls the future.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The caller must ensure it is safe to mutate the `state` field. This
|
||||
/// requires ensuring mutual exclusion between any concurrent thread that
|
||||
/// might modify the future or output field.
|
||||
///
|
||||
/// The mutual exclusion is implemented by `Harness` and the `Lifecycle`
|
||||
/// component of the task state.
|
||||
///
|
||||
/// `self` must also be pinned. This is handled by storing the task on the
|
||||
/// heap.
|
||||
pub(super) fn poll(&self, mut cx: Context<'_>) -> Poll<T::Output> {
|
||||
let res = {
|
||||
self.stage.stage.with_mut(|ptr| {
|
||||
// Safety: The caller ensures mutual exclusion to the field.
|
||||
let future = match unsafe { &mut *ptr } {
|
||||
Stage::Running(future) => future,
|
||||
_ => unreachable!("unexpected stage"),
|
||||
};
|
||||
|
||||
// Safety: The caller ensures the future is pinned.
|
||||
let future = unsafe { Pin::new_unchecked(future) };
|
||||
|
||||
let _guard = TaskIdGuard::enter(self.task_id);
|
||||
future.poll(&mut cx)
|
||||
})
|
||||
};
|
||||
|
||||
if res.is_ready() {
|
||||
self.drop_future_or_output();
|
||||
}
|
||||
|
||||
res
|
||||
}
|
||||
|
||||
/// Drops the future.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The caller must ensure it is safe to mutate the `stage` field.
|
||||
pub(super) fn drop_future_or_output(&self) {
|
||||
// Safety: the caller ensures mutual exclusion to the field.
|
||||
unsafe {
|
||||
self.set_stage(Stage::Consumed);
|
||||
}
|
||||
}
|
||||
|
||||
/// Stores the task output.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The caller must ensure it is safe to mutate the `stage` field.
|
||||
pub(super) fn store_output(&self, output: super::Result<T::Output>) {
|
||||
// Safety: the caller ensures mutual exclusion to the field.
|
||||
unsafe {
|
||||
self.set_stage(Stage::Finished(output));
|
||||
}
|
||||
}
|
||||
|
||||
/// Takes the task output.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The caller must ensure it is safe to mutate the `stage` field.
|
||||
pub(super) fn take_output(&self) -> super::Result<T::Output> {
|
||||
use std::mem;
|
||||
|
||||
self.stage.stage.with_mut(|ptr| {
|
||||
// Safety:: the caller ensures mutual exclusion to the field.
|
||||
match mem::replace(unsafe { &mut *ptr }, Stage::Consumed) {
|
||||
Stage::Finished(output) => output,
|
||||
_ => panic!("JoinHandle polled after completion"),
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
unsafe fn set_stage(&self, stage: Stage<T>) {
|
||||
let _guard = TaskIdGuard::enter(self.task_id);
|
||||
self.stage.stage.with_mut(|ptr| *ptr = stage);
|
||||
}
|
||||
}
|
||||
|
||||
impl Header {
|
||||
pub(super) unsafe fn set_next(&self, next: Option<NonNull<Header>>) {
|
||||
self.queue_next.with_mut(|ptr| *ptr = next);
|
||||
}
|
||||
|
||||
// safety: The caller must guarantee exclusive access to this field, and
|
||||
// must ensure that the id is either `None` or the id of the OwnedTasks
|
||||
// containing this task.
|
||||
pub(super) unsafe fn set_owner_id(&self, owner: NonZeroU64) {
|
||||
self.owner_id.with_mut(|ptr| *ptr = Some(owner));
|
||||
}
|
||||
|
||||
pub(super) fn get_owner_id(&self) -> Option<NonZeroU64> {
|
||||
// safety: If there are concurrent writes, then that write has violated
|
||||
// the safety requirements on `set_owner_id`.
|
||||
unsafe { self.owner_id.with(|ptr| *ptr) }
|
||||
}
|
||||
|
||||
/// Gets a pointer to the `Trailer` of the task containing this `Header`.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The provided raw pointer must point at the header of a task.
|
||||
pub(super) unsafe fn get_trailer(me: NonNull<Header>) -> NonNull<Trailer> {
|
||||
let offset = me.as_ref().vtable.trailer_offset;
|
||||
let trailer = me.as_ptr().cast::<u8>().add(offset).cast::<Trailer>();
|
||||
NonNull::new_unchecked(trailer)
|
||||
}
|
||||
|
||||
/// Gets a pointer to the scheduler of the task containing this `Header`.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The provided raw pointer must point at the header of a task.
|
||||
///
|
||||
/// The generic type S must be set to the correct scheduler type for this
|
||||
/// task.
|
||||
pub(super) unsafe fn get_scheduler<S>(me: NonNull<Header>) -> NonNull<S> {
|
||||
let offset = me.as_ref().vtable.scheduler_offset;
|
||||
let scheduler = me.as_ptr().cast::<u8>().add(offset).cast::<S>();
|
||||
NonNull::new_unchecked(scheduler)
|
||||
}
|
||||
|
||||
/// Gets a pointer to the id of the task containing this `Header`.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The provided raw pointer must point at the header of a task.
|
||||
pub(super) unsafe fn get_id_ptr(me: NonNull<Header>) -> NonNull<Id> {
|
||||
let offset = me.as_ref().vtable.id_offset;
|
||||
let id = me.as_ptr().cast::<u8>().add(offset).cast::<Id>();
|
||||
NonNull::new_unchecked(id)
|
||||
}
|
||||
|
||||
/// Gets the id of the task containing this `Header`.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The provided raw pointer must point at the header of a task.
|
||||
pub(super) unsafe fn get_id(me: NonNull<Header>) -> Id {
|
||||
let ptr = Header::get_id_ptr(me).as_ptr();
|
||||
*ptr
|
||||
}
|
||||
|
||||
/// Gets a pointer to the source code location where the task containing
|
||||
/// this `Header` was spawned.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The provided raw pointer must point at the header of a task.
|
||||
#[cfg(tokio_unstable)]
|
||||
pub(super) unsafe fn get_spawn_location_ptr(
|
||||
me: NonNull<Header>,
|
||||
) -> NonNull<&'static Location<'static>> {
|
||||
let offset = me.as_ref().vtable.spawn_location_offset;
|
||||
let spawned_at = me
|
||||
.as_ptr()
|
||||
.cast::<u8>()
|
||||
.add(offset)
|
||||
.cast::<&'static Location<'static>>();
|
||||
NonNull::new_unchecked(spawned_at)
|
||||
}
|
||||
|
||||
/// Gets the source code location where the task containing
|
||||
/// this `Header` was spawned
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The provided raw pointer must point at the header of a task.
|
||||
#[cfg(tokio_unstable)]
|
||||
pub(super) unsafe fn get_spawn_location(me: NonNull<Header>) -> &'static Location<'static> {
|
||||
let ptr = Header::get_spawn_location_ptr(me).as_ptr();
|
||||
*ptr
|
||||
}
|
||||
|
||||
/// Gets the tracing id of the task containing this `Header`.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The provided raw pointer must point at the header of a task.
|
||||
#[cfg(all(tokio_unstable, feature = "tracing"))]
|
||||
pub(super) unsafe fn get_tracing_id(me: &NonNull<Header>) -> Option<&tracing::Id> {
|
||||
me.as_ref().tracing_id.as_ref()
|
||||
}
|
||||
}
|
||||
|
||||
impl Trailer {
|
||||
fn new(hooks: TaskHarnessScheduleHooks) -> Self {
|
||||
Trailer {
|
||||
waker: UnsafeCell::new(None),
|
||||
owned: linked_list::Pointers::new(),
|
||||
hooks,
|
||||
}
|
||||
}
|
||||
|
||||
pub(super) unsafe fn set_waker(&self, waker: Option<Waker>) {
|
||||
self.waker.with_mut(|ptr| {
|
||||
*ptr = waker;
|
||||
});
|
||||
}
|
||||
|
||||
pub(super) unsafe fn will_wake(&self, waker: &Waker) -> bool {
|
||||
self.waker
|
||||
.with(|ptr| (*ptr).as_ref().unwrap().will_wake(waker))
|
||||
}
|
||||
|
||||
pub(super) fn wake_join(&self) {
|
||||
self.waker.with(|ptr| match unsafe { &*ptr } {
|
||||
Some(waker) => waker.wake_by_ref(),
|
||||
None => panic!("waker missing"),
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[cfg(not(loom))]
|
||||
fn header_lte_cache_line() {
|
||||
assert!(std::mem::size_of::<Header>() <= 8 * std::mem::size_of::<*const ()>());
|
||||
}
|
||||
@@ -1,159 +0,0 @@
|
||||
# Copyright 2012-2022 The Meson development team
|
||||
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
"""
|
||||
Contains the strict minimum to run scripts.
|
||||
|
||||
When the backend needs to call back into Meson during compilation for running
|
||||
scripts or wrapping commands, it is important to load as little python modules
|
||||
as possible for performance reasons.
|
||||
"""
|
||||
|
||||
from __future__ import annotations
|
||||
from dataclasses import dataclass
|
||||
import os
|
||||
import abc
|
||||
import typing as T
|
||||
|
||||
if T.TYPE_CHECKING:
|
||||
from hashlib import _Hash
|
||||
from typing_extensions import Literal
|
||||
from ..mparser import BaseNode
|
||||
from .. import programs
|
||||
|
||||
EnvironOrDict = T.Union[T.Dict[str, str], os._Environ[str]]
|
||||
|
||||
EnvInitValueType = T.Dict[str, T.Union[str, T.List[str]]]
|
||||
|
||||
|
||||
class MesonException(Exception):
|
||||
'''Exceptions thrown by Meson'''
|
||||
|
||||
def __init__(self, *args: object, file: T.Optional[str] = None,
|
||||
lineno: T.Optional[int] = None, colno: T.Optional[int] = None):
|
||||
super().__init__(*args)
|
||||
self.file = file
|
||||
self.lineno = lineno
|
||||
self.colno = colno
|
||||
|
||||
@classmethod
|
||||
def from_node(cls, *args: object, node: BaseNode) -> MesonException:
|
||||
"""Create a MesonException with location data from a BaseNode
|
||||
|
||||
:param node: A BaseNode to set location data from
|
||||
:return: A Meson Exception instance
|
||||
"""
|
||||
return cls(*args, file=node.filename, lineno=node.lineno, colno=node.colno)
|
||||
|
||||
class MesonBugException(MesonException):
|
||||
'''Exceptions thrown when there is a clear Meson bug that should be reported'''
|
||||
|
||||
def __init__(self, msg: str, file: T.Optional[str] = None,
|
||||
lineno: T.Optional[int] = None, colno: T.Optional[int] = None):
|
||||
super().__init__(msg + '\n\n This is a Meson bug and should be reported!',
|
||||
file=file, lineno=lineno, colno=colno)
|
||||
|
||||
class HoldableObject(metaclass=abc.ABCMeta):
|
||||
''' Dummy base class for all objects that can be
|
||||
held by an interpreter.baseobjects.ObjectHolder '''
|
||||
|
||||
class EnvironmentVariables(HoldableObject):
|
||||
def __init__(self, values: T.Optional[EnvInitValueType] = None,
|
||||
init_method: Literal['set', 'prepend', 'append'] = 'set', separator: str = os.pathsep) -> None:
|
||||
self.envvars: T.List[T.Tuple[T.Callable[[T.Dict[str, str], str, T.List[str], str, T.Optional[str]], str], str, T.List[str], str]] = []
|
||||
# The set of all env vars we have operations for. Only used for self.has_name()
|
||||
self.varnames: T.Set[str] = set()
|
||||
|
||||
if values:
|
||||
init_func = getattr(self, init_method)
|
||||
for name, value in values.items():
|
||||
v = value if isinstance(value, list) else [value]
|
||||
init_func(name, v, separator)
|
||||
|
||||
def __repr__(self) -> str:
|
||||
repr_str = "<{0}: {1}>"
|
||||
return repr_str.format(self.__class__.__name__, self.envvars)
|
||||
|
||||
def hash(self, hasher: _Hash) -> None:
|
||||
myenv = self.get_env({})
|
||||
for key in sorted(myenv.keys()):
|
||||
hasher.update(bytes(key, encoding='utf-8'))
|
||||
hasher.update(b',')
|
||||
hasher.update(bytes(myenv[key], encoding='utf-8'))
|
||||
hasher.update(b';')
|
||||
|
||||
def has_name(self, name: str) -> bool:
|
||||
return name in self.varnames
|
||||
|
||||
def get_names(self) -> T.Set[str]:
|
||||
return self.varnames
|
||||
|
||||
def merge(self, other: EnvironmentVariables) -> None:
|
||||
for method, name, values, separator in other.envvars:
|
||||
self.varnames.add(name)
|
||||
self.envvars.append((method, name, values, separator))
|
||||
|
||||
def set(self, name: str, values: T.List[str], separator: str = os.pathsep) -> None:
|
||||
self.varnames.add(name)
|
||||
self.envvars.append((self._set, name, values, separator))
|
||||
|
||||
def append(self, name: str, values: T.List[str], separator: str = os.pathsep) -> None:
|
||||
self.varnames.add(name)
|
||||
self.envvars.append((self._append, name, values, separator))
|
||||
|
||||
def prepend(self, name: str, values: T.List[str], separator: str = os.pathsep) -> None:
|
||||
self.varnames.add(name)
|
||||
self.envvars.append((self._prepend, name, values, separator))
|
||||
|
||||
@staticmethod
|
||||
def _set(env: T.Dict[str, str], name: str, values: T.List[str], separator: str, default_value: T.Optional[str]) -> str:
|
||||
return separator.join(values)
|
||||
|
||||
@staticmethod
|
||||
def _append(env: T.Dict[str, str], name: str, values: T.List[str], separator: str, default_value: T.Optional[str]) -> str:
|
||||
curr = env.get(name, default_value)
|
||||
return separator.join(values if curr is None else [curr] + values)
|
||||
|
||||
@staticmethod
|
||||
def _prepend(env: T.Dict[str, str], name: str, values: T.List[str], separator: str, default_value: T.Optional[str]) -> str:
|
||||
curr = env.get(name, default_value)
|
||||
return separator.join(values if curr is None else values + [curr])
|
||||
|
||||
def get_env(self, full_env: EnvironOrDict, default_fmt: T.Optional[str] = None) -> T.Dict[str, str]:
|
||||
env = full_env.copy()
|
||||
for method, name, values, separator in self.envvars:
|
||||
default_value = default_fmt.format(name) if default_fmt else None
|
||||
env[name] = method(env, name, values, separator, default_value)
|
||||
return env
|
||||
|
||||
|
||||
@dataclass(eq=False)
|
||||
class ExecutableSerialisation:
|
||||
|
||||
cmd_args: T.List[str]
|
||||
env: T.Optional[EnvironmentVariables] = None
|
||||
exe_wrapper: T.Optional['programs.ExternalProgram'] = None
|
||||
workdir: T.Optional[str] = None
|
||||
extra_paths: T.Optional[T.List] = None
|
||||
capture: T.Optional[str] = None
|
||||
feed: T.Optional[str] = None
|
||||
tag: T.Optional[str] = None
|
||||
verbose: bool = False
|
||||
installdir_map: T.Optional[T.Dict[str, str]] = None
|
||||
|
||||
def __post_init__(self) -> None:
|
||||
self.pickled = False
|
||||
self.skip_if_destdir = False
|
||||
self.subproject = ''
|
||||
self.dry_run = False
|
||||
@@ -1,9 +0,0 @@
|
||||
#include <xdg-shell-client-protocol.h>
|
||||
|
||||
int main() {
|
||||
#if defined(XDG_SHELL_CLIENT_PROTOCOL_H) && !defined(WAYLAND_CLIENT_H) && !defined(WAYLAND_CLIENT_PROTOCOL_H)
|
||||
return 0;
|
||||
#else
|
||||
return 1;
|
||||
#endif
|
||||
}
|
||||
@@ -1,64 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
|
||||
/*
|
||||
* linux/can/core.h
|
||||
*
|
||||
* Prototypes and definitions for CAN protocol modules using the PF_CAN core
|
||||
*
|
||||
* Authors: Oliver Hartkopp <oliver.hartkopp@volkswagen.de>
|
||||
* Urs Thuermann <urs.thuermann@volkswagen.de>
|
||||
* Copyright (c) 2002-2017 Volkswagen Group Electronic Research
|
||||
* All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _CAN_CORE_H
|
||||
#define _CAN_CORE_H
|
||||
|
||||
#include <linux/can.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/netdevice.h>
|
||||
|
||||
#define DNAME(dev) ((dev) ? (dev)->name : "any")
|
||||
|
||||
/**
|
||||
* struct can_proto - CAN protocol structure
|
||||
* @type: type argument in socket() syscall, e.g. SOCK_DGRAM.
|
||||
* @protocol: protocol number in socket() syscall.
|
||||
* @ops: pointer to struct proto_ops for sock->ops.
|
||||
* @prot: pointer to struct proto structure.
|
||||
*/
|
||||
struct can_proto {
|
||||
int type;
|
||||
int protocol;
|
||||
const struct proto_ops *ops;
|
||||
struct proto *prot;
|
||||
};
|
||||
|
||||
/* required_size
|
||||
* macro to find the minimum size of a struct
|
||||
* that includes a requested member
|
||||
*/
|
||||
#define CAN_REQUIRED_SIZE(struct_type, member) \
|
||||
(offsetof(typeof(struct_type), member) + \
|
||||
sizeof(((typeof(struct_type) *)(NULL))->member))
|
||||
|
||||
/* function prototypes for the CAN networklayer core (af_can.c) */
|
||||
|
||||
extern int can_proto_register(const struct can_proto *cp);
|
||||
extern void can_proto_unregister(const struct can_proto *cp);
|
||||
|
||||
int can_rx_register(struct net *net, struct net_device *dev,
|
||||
canid_t can_id, canid_t mask,
|
||||
void (*func)(struct sk_buff *, void *),
|
||||
void *data, char *ident, struct sock *sk);
|
||||
|
||||
extern void can_rx_unregister(struct net *net, struct net_device *dev,
|
||||
canid_t can_id, canid_t mask,
|
||||
void (*func)(struct sk_buff *, void *),
|
||||
void *data);
|
||||
|
||||
extern int can_send(struct sk_buff *skb, int loop);
|
||||
void can_set_skb_uid(struct sk_buff *skb);
|
||||
void can_sock_destruct(struct sock *sk);
|
||||
|
||||
#endif /* !_CAN_CORE_H */
|
||||
@@ -1,191 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Arizona MFD internals
|
||||
*
|
||||
* Copyright 2012 Wolfson Microelectronics plc
|
||||
*
|
||||
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
*/
|
||||
|
||||
#ifndef _WM_ARIZONA_CORE_H
|
||||
#define _WM_ARIZONA_CORE_H
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/mfd/arizona/pdata.h>
|
||||
|
||||
#define ARIZONA_MAX_CORE_SUPPLIES 2
|
||||
|
||||
enum {
|
||||
ARIZONA_MCLK1,
|
||||
ARIZONA_MCLK2,
|
||||
ARIZONA_NUM_MCLK
|
||||
};
|
||||
|
||||
enum arizona_type {
|
||||
WM5102 = 1,
|
||||
WM5110 = 2,
|
||||
WM8997 = 3,
|
||||
WM8280 = 4,
|
||||
WM8998 = 5,
|
||||
WM1814 = 6,
|
||||
WM1831 = 7,
|
||||
CS47L24 = 8,
|
||||
};
|
||||
|
||||
#define ARIZONA_IRQ_GP1 0
|
||||
#define ARIZONA_IRQ_GP2 1
|
||||
#define ARIZONA_IRQ_GP3 2
|
||||
#define ARIZONA_IRQ_GP4 3
|
||||
#define ARIZONA_IRQ_GP5_FALL 4
|
||||
#define ARIZONA_IRQ_GP5_RISE 5
|
||||
#define ARIZONA_IRQ_JD_FALL 6
|
||||
#define ARIZONA_IRQ_JD_RISE 7
|
||||
#define ARIZONA_IRQ_DSP1_RAM_RDY 8
|
||||
#define ARIZONA_IRQ_DSP2_RAM_RDY 9
|
||||
#define ARIZONA_IRQ_DSP3_RAM_RDY 10
|
||||
#define ARIZONA_IRQ_DSP4_RAM_RDY 11
|
||||
#define ARIZONA_IRQ_DSP_IRQ1 12
|
||||
#define ARIZONA_IRQ_DSP_IRQ2 13
|
||||
#define ARIZONA_IRQ_DSP_IRQ3 14
|
||||
#define ARIZONA_IRQ_DSP_IRQ4 15
|
||||
#define ARIZONA_IRQ_DSP_IRQ5 16
|
||||
#define ARIZONA_IRQ_DSP_IRQ6 17
|
||||
#define ARIZONA_IRQ_DSP_IRQ7 18
|
||||
#define ARIZONA_IRQ_DSP_IRQ8 19
|
||||
#define ARIZONA_IRQ_SPK_OVERHEAT_WARN 20
|
||||
#define ARIZONA_IRQ_SPK_OVERHEAT 21
|
||||
#define ARIZONA_IRQ_MICDET 22
|
||||
#define ARIZONA_IRQ_HPDET 23
|
||||
#define ARIZONA_IRQ_WSEQ_DONE 24
|
||||
#define ARIZONA_IRQ_DRC2_SIG_DET 25
|
||||
#define ARIZONA_IRQ_DRC1_SIG_DET 26
|
||||
#define ARIZONA_IRQ_ASRC2_LOCK 27
|
||||
#define ARIZONA_IRQ_ASRC1_LOCK 28
|
||||
#define ARIZONA_IRQ_UNDERCLOCKED 29
|
||||
#define ARIZONA_IRQ_OVERCLOCKED 30
|
||||
#define ARIZONA_IRQ_FLL2_LOCK 31
|
||||
#define ARIZONA_IRQ_FLL1_LOCK 32
|
||||
#define ARIZONA_IRQ_CLKGEN_ERR 33
|
||||
#define ARIZONA_IRQ_CLKGEN_ERR_ASYNC 34
|
||||
#define ARIZONA_IRQ_ASRC_CFG_ERR 35
|
||||
#define ARIZONA_IRQ_AIF3_ERR 36
|
||||
#define ARIZONA_IRQ_AIF2_ERR 37
|
||||
#define ARIZONA_IRQ_AIF1_ERR 38
|
||||
#define ARIZONA_IRQ_CTRLIF_ERR 39
|
||||
#define ARIZONA_IRQ_MIXER_DROPPED_SAMPLES 40
|
||||
#define ARIZONA_IRQ_ASYNC_CLK_ENA_LOW 41
|
||||
#define ARIZONA_IRQ_SYSCLK_ENA_LOW 42
|
||||
#define ARIZONA_IRQ_ISRC1_CFG_ERR 43
|
||||
#define ARIZONA_IRQ_ISRC2_CFG_ERR 44
|
||||
#define ARIZONA_IRQ_BOOT_DONE 45
|
||||
#define ARIZONA_IRQ_DCS_DAC_DONE 46
|
||||
#define ARIZONA_IRQ_DCS_HP_DONE 47
|
||||
#define ARIZONA_IRQ_FLL2_CLOCK_OK 48
|
||||
#define ARIZONA_IRQ_FLL1_CLOCK_OK 49
|
||||
#define ARIZONA_IRQ_MICD_CLAMP_RISE 50
|
||||
#define ARIZONA_IRQ_MICD_CLAMP_FALL 51
|
||||
#define ARIZONA_IRQ_HP3R_DONE 52
|
||||
#define ARIZONA_IRQ_HP3L_DONE 53
|
||||
#define ARIZONA_IRQ_HP2R_DONE 54
|
||||
#define ARIZONA_IRQ_HP2L_DONE 55
|
||||
#define ARIZONA_IRQ_HP1R_DONE 56
|
||||
#define ARIZONA_IRQ_HP1L_DONE 57
|
||||
#define ARIZONA_IRQ_ISRC3_CFG_ERR 58
|
||||
#define ARIZONA_IRQ_DSP_SHARED_WR_COLL 59
|
||||
#define ARIZONA_IRQ_SPK_SHUTDOWN 60
|
||||
#define ARIZONA_IRQ_SPK1R_SHORT 61
|
||||
#define ARIZONA_IRQ_SPK1L_SHORT 62
|
||||
#define ARIZONA_IRQ_HP3R_SC_NEG 63
|
||||
#define ARIZONA_IRQ_HP3R_SC_POS 64
|
||||
#define ARIZONA_IRQ_HP3L_SC_NEG 65
|
||||
#define ARIZONA_IRQ_HP3L_SC_POS 66
|
||||
#define ARIZONA_IRQ_HP2R_SC_NEG 67
|
||||
#define ARIZONA_IRQ_HP2R_SC_POS 68
|
||||
#define ARIZONA_IRQ_HP2L_SC_NEG 69
|
||||
#define ARIZONA_IRQ_HP2L_SC_POS 70
|
||||
#define ARIZONA_IRQ_HP1R_SC_NEG 71
|
||||
#define ARIZONA_IRQ_HP1R_SC_POS 72
|
||||
#define ARIZONA_IRQ_HP1L_SC_NEG 73
|
||||
#define ARIZONA_IRQ_HP1L_SC_POS 74
|
||||
|
||||
#define ARIZONA_NUM_IRQ 75
|
||||
|
||||
struct snd_soc_dapm_context;
|
||||
|
||||
struct arizona {
|
||||
struct regmap *regmap;
|
||||
struct device *dev;
|
||||
|
||||
enum arizona_type type;
|
||||
unsigned int rev;
|
||||
|
||||
int num_core_supplies;
|
||||
struct regulator_bulk_data core_supplies[ARIZONA_MAX_CORE_SUPPLIES];
|
||||
struct regulator *dcvdd;
|
||||
bool has_fully_powered_off;
|
||||
|
||||
struct arizona_pdata pdata;
|
||||
|
||||
unsigned int external_dcvdd:1;
|
||||
|
||||
int irq;
|
||||
struct irq_domain *virq;
|
||||
struct regmap_irq_chip_data *aod_irq_chip;
|
||||
struct regmap_irq_chip_data *irq_chip;
|
||||
|
||||
bool hpdet_clamp;
|
||||
unsigned int hp_ena;
|
||||
|
||||
struct mutex clk_lock;
|
||||
int clk32k_ref;
|
||||
|
||||
struct clk *mclk[ARIZONA_NUM_MCLK];
|
||||
|
||||
bool ctrlif_error;
|
||||
|
||||
struct snd_soc_dapm_context *dapm;
|
||||
|
||||
int tdm_width[ARIZONA_MAX_AIF];
|
||||
int tdm_slots[ARIZONA_MAX_AIF];
|
||||
|
||||
uint16_t dac_comp_coeff;
|
||||
uint8_t dac_comp_enabled;
|
||||
struct mutex dac_comp_lock;
|
||||
|
||||
struct blocking_notifier_head notifier;
|
||||
};
|
||||
|
||||
static inline int arizona_call_notifiers(struct arizona *arizona,
|
||||
unsigned long event,
|
||||
void *data)
|
||||
{
|
||||
return blocking_notifier_call_chain(&arizona->notifier, event, data);
|
||||
}
|
||||
|
||||
int arizona_clk32k_enable(struct arizona *arizona);
|
||||
int arizona_clk32k_disable(struct arizona *arizona);
|
||||
|
||||
int arizona_request_irq(struct arizona *arizona, int irq, char *name,
|
||||
irq_handler_t handler, void *data);
|
||||
void arizona_free_irq(struct arizona *arizona, int irq, void *data);
|
||||
int arizona_set_irq_wake(struct arizona *arizona, int irq, int on);
|
||||
|
||||
#ifdef CONFIG_MFD_WM5102
|
||||
int wm5102_patch(struct arizona *arizona);
|
||||
#else
|
||||
static inline int wm5102_patch(struct arizona *arizona)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int wm5110_patch(struct arizona *arizona);
|
||||
int cs47l24_patch(struct arizona *arizona);
|
||||
int wm8997_patch(struct arizona *arizona);
|
||||
int wm8998_patch(struct arizona *arizona);
|
||||
|
||||
#endif
|
||||
@@ -1,58 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Core MFD defines for ATC260x PMICs
|
||||
*
|
||||
* Copyright (C) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
* Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_ATC260X_CORE_H
|
||||
#define __LINUX_MFD_ATC260X_CORE_H
|
||||
|
||||
#include <linux/mfd/atc260x/atc2603c.h>
|
||||
#include <linux/mfd/atc260x/atc2609a.h>
|
||||
|
||||
enum atc260x_type {
|
||||
ATC2603A = 0,
|
||||
ATC2603C,
|
||||
ATC2609A,
|
||||
};
|
||||
|
||||
enum atc260x_ver {
|
||||
ATC260X_A = 0,
|
||||
ATC260X_B,
|
||||
ATC260X_C,
|
||||
ATC260X_D,
|
||||
ATC260X_E,
|
||||
ATC260X_F,
|
||||
ATC260X_G,
|
||||
ATC260X_H,
|
||||
};
|
||||
|
||||
struct atc260x {
|
||||
struct device *dev;
|
||||
|
||||
struct regmap *regmap;
|
||||
const struct regmap_irq_chip *regmap_irq_chip;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
|
||||
struct mutex *regmap_mutex; /* mutex for custom regmap locking */
|
||||
|
||||
const struct mfd_cell *cells;
|
||||
int nr_cells;
|
||||
int irq;
|
||||
|
||||
enum atc260x_type ic_type;
|
||||
enum atc260x_ver ic_ver;
|
||||
const char *type_name;
|
||||
unsigned int rev_reg;
|
||||
|
||||
const struct atc260x_init_regs *init_regs; /* regs for device init */
|
||||
};
|
||||
|
||||
struct regmap_config;
|
||||
|
||||
int atc260x_match_device(struct atc260x *atc260x, struct regmap_config *regmap_cfg);
|
||||
int atc260x_device_probe(struct atc260x *atc260x);
|
||||
|
||||
#endif /* __LINUX_MFD_ATC260X_CORE_H */
|
||||
@@ -1,151 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* drivers/mfd/mfd-core.h
|
||||
*
|
||||
* core MFD support
|
||||
* Copyright (c) 2006 Ian Molton
|
||||
* Copyright (c) 2007 Dmitry Baryshkov
|
||||
*/
|
||||
|
||||
#ifndef MFD_CORE_H
|
||||
#define MFD_CORE_H
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#define MFD_RES_SIZE(arr) (sizeof(arr) / sizeof(struct resource))
|
||||
|
||||
#define MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, _use_of_reg, _match) \
|
||||
{ \
|
||||
.name = (_name), \
|
||||
.resources = (_res), \
|
||||
.num_resources = MFD_RES_SIZE((_res)), \
|
||||
.platform_data = (_pdata), \
|
||||
.pdata_size = (_pdsize), \
|
||||
.of_compatible = (_compat), \
|
||||
.of_reg = (_of_reg), \
|
||||
.use_of_reg = (_use_of_reg), \
|
||||
.acpi_match = (_match), \
|
||||
.id = (_id), \
|
||||
}
|
||||
|
||||
#define MFD_CELL_OF_REG(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg) \
|
||||
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, true, NULL)
|
||||
|
||||
#define MFD_CELL_OF(_name, _res, _pdata, _pdsize, _id, _compat) \
|
||||
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, 0, false, NULL)
|
||||
|
||||
#define MFD_CELL_ACPI(_name, _res, _pdata, _pdsize, _id, _match) \
|
||||
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, _match)
|
||||
|
||||
#define MFD_CELL_BASIC(_name, _res, _pdata, _pdsize, _id) \
|
||||
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, NULL)
|
||||
|
||||
#define MFD_CELL_RES(_name, _res) \
|
||||
MFD_CELL_ALL(_name, _res, NULL, 0, 0, NULL, 0, false, NULL)
|
||||
|
||||
#define MFD_CELL_NAME(_name) \
|
||||
MFD_CELL_ALL(_name, NULL, NULL, 0, 0, NULL, 0, false, NULL)
|
||||
|
||||
#define MFD_DEP_LEVEL_NORMAL 0
|
||||
#define MFD_DEP_LEVEL_HIGH 1
|
||||
|
||||
struct irq_domain;
|
||||
struct software_node;
|
||||
|
||||
/* Matches ACPI PNP id, either _HID or _CID, or ACPI _ADR */
|
||||
struct mfd_cell_acpi_match {
|
||||
const char *pnpid;
|
||||
const unsigned long long adr;
|
||||
};
|
||||
|
||||
/*
|
||||
* This struct describes the MFD part ("cell").
|
||||
* After registration the copy of this structure will become the platform data
|
||||
* of the resulting platform_device
|
||||
*/
|
||||
struct mfd_cell {
|
||||
const char *name;
|
||||
int id;
|
||||
int level;
|
||||
|
||||
int (*suspend)(struct platform_device *dev);
|
||||
int (*resume)(struct platform_device *dev);
|
||||
|
||||
/* platform data passed to the sub devices drivers */
|
||||
const void *platform_data;
|
||||
size_t pdata_size;
|
||||
|
||||
/* Matches ACPI */
|
||||
const struct mfd_cell_acpi_match *acpi_match;
|
||||
|
||||
/* Software node for the device. */
|
||||
const struct software_node *swnode;
|
||||
|
||||
/*
|
||||
* Device Tree compatible string
|
||||
* See: Documentation/devicetree/usage-model.rst Chapter 2.2 for details
|
||||
*/
|
||||
const char *of_compatible;
|
||||
|
||||
/*
|
||||
* Address as defined in Device Tree. Used to complement 'of_compatible'
|
||||
* (above) when matching OF nodes with devices that have identical
|
||||
* compatible strings
|
||||
*/
|
||||
u64 of_reg;
|
||||
|
||||
/* Set to 'true' to use 'of_reg' (above) - allows for of_reg=0 */
|
||||
bool use_of_reg;
|
||||
|
||||
/*
|
||||
* These resources can be specified relative to the parent device.
|
||||
* For accessing hardware you should use resources from the platform dev
|
||||
*/
|
||||
int num_resources;
|
||||
const struct resource *resources;
|
||||
|
||||
/* don't check for resource conflicts */
|
||||
bool ignore_resource_conflicts;
|
||||
|
||||
/*
|
||||
* Disable runtime PM callbacks for this subdevice - see
|
||||
* pm_runtime_no_callbacks().
|
||||
*/
|
||||
bool pm_runtime_no_callbacks;
|
||||
|
||||
/* A list of regulator supplies that should be mapped to the MFD
|
||||
* device rather than the child device when requested
|
||||
*/
|
||||
int num_parent_supplies;
|
||||
const char * const *parent_supplies;
|
||||
};
|
||||
|
||||
/*
|
||||
* Given a platform device that's been created by mfd_add_devices(), fetch
|
||||
* the mfd_cell that created it.
|
||||
*/
|
||||
static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev)
|
||||
{
|
||||
return pdev->mfd_cell;
|
||||
}
|
||||
|
||||
extern int mfd_add_devices(struct device *parent, int id,
|
||||
const struct mfd_cell *cells, int n_devs,
|
||||
struct resource *mem_base,
|
||||
int irq_base, struct irq_domain *irq_domain);
|
||||
|
||||
static inline int mfd_add_hotplug_devices(struct device *parent,
|
||||
const struct mfd_cell *cells, int n_devs)
|
||||
{
|
||||
return mfd_add_devices(parent, PLATFORM_DEVID_AUTO, cells, n_devs,
|
||||
NULL, 0, NULL);
|
||||
}
|
||||
|
||||
extern void mfd_remove_devices(struct device *parent);
|
||||
extern void mfd_remove_devices_late(struct device *parent);
|
||||
|
||||
extern int devm_mfd_add_devices(struct device *dev, int id,
|
||||
const struct mfd_cell *cells, int n_devs,
|
||||
struct resource *mem_base,
|
||||
int irq_base, struct irq_domain *irq_domain);
|
||||
#endif
|
||||
@@ -1,80 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* da9055 declarations for DA9055 PMICs.
|
||||
*
|
||||
* Copyright(c) 2012 Dialog Semiconductor Ltd.
|
||||
*
|
||||
* Author: David Dajun Chen <dchen@diasemi.com>
|
||||
*/
|
||||
|
||||
#ifndef __DA9055_CORE_H
|
||||
#define __DA9055_CORE_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
/*
|
||||
* PMIC IRQ
|
||||
*/
|
||||
#define DA9055_IRQ_ALARM 0x01
|
||||
#define DA9055_IRQ_TICK 0x02
|
||||
#define DA9055_IRQ_NONKEY 0x00
|
||||
#define DA9055_IRQ_REGULATOR 0x0B
|
||||
#define DA9055_IRQ_HWMON 0x03
|
||||
|
||||
struct da9055_pdata;
|
||||
|
||||
struct da9055 {
|
||||
struct regmap *regmap;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
struct device *dev;
|
||||
struct i2c_client *i2c_client;
|
||||
|
||||
int irq_base;
|
||||
int chip_irq;
|
||||
};
|
||||
|
||||
/* Device I/O */
|
||||
static inline int da9055_reg_read(struct da9055 *da9055, unsigned char reg)
|
||||
{
|
||||
int val, ret;
|
||||
|
||||
ret = regmap_read(da9055->regmap, reg, &val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline int da9055_reg_write(struct da9055 *da9055, unsigned char reg,
|
||||
unsigned char val)
|
||||
{
|
||||
return regmap_write(da9055->regmap, reg, val);
|
||||
}
|
||||
|
||||
static inline int da9055_group_read(struct da9055 *da9055, unsigned char reg,
|
||||
unsigned reg_cnt, unsigned char *val)
|
||||
{
|
||||
return regmap_bulk_read(da9055->regmap, reg, val, reg_cnt);
|
||||
}
|
||||
|
||||
static inline int da9055_group_write(struct da9055 *da9055, unsigned char reg,
|
||||
unsigned reg_cnt, unsigned char *val)
|
||||
{
|
||||
return regmap_raw_write(da9055->regmap, reg, val, reg_cnt);
|
||||
}
|
||||
|
||||
static inline int da9055_reg_update(struct da9055 *da9055, unsigned char reg,
|
||||
unsigned char bit_mask,
|
||||
unsigned char reg_val)
|
||||
{
|
||||
return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val);
|
||||
}
|
||||
|
||||
/* Generic Device API */
|
||||
int da9055_device_init(struct da9055 *da9055);
|
||||
void da9055_device_exit(struct da9055 *da9055);
|
||||
|
||||
extern const struct regmap_config da9055_regmap_config;
|
||||
|
||||
#endif /* __DA9055_CORE_H */
|
||||
@@ -1,66 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Dialog Semiconductor
|
||||
*/
|
||||
|
||||
#ifndef __MFD_DA9062_CORE_H__
|
||||
#define __MFD_DA9062_CORE_H__
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mfd/da9062/registers.h>
|
||||
|
||||
enum da9062_compatible_types {
|
||||
COMPAT_TYPE_DA9061 = 1,
|
||||
COMPAT_TYPE_DA9062,
|
||||
};
|
||||
|
||||
enum da9061_irqs {
|
||||
/* IRQ A */
|
||||
DA9061_IRQ_ONKEY,
|
||||
DA9061_IRQ_WDG_WARN,
|
||||
DA9061_IRQ_SEQ_RDY,
|
||||
/* IRQ B*/
|
||||
DA9061_IRQ_TEMP,
|
||||
DA9061_IRQ_LDO_LIM,
|
||||
DA9061_IRQ_DVC_RDY,
|
||||
DA9061_IRQ_VDD_WARN,
|
||||
/* IRQ C */
|
||||
DA9061_IRQ_GPI0,
|
||||
DA9061_IRQ_GPI1,
|
||||
DA9061_IRQ_GPI2,
|
||||
DA9061_IRQ_GPI3,
|
||||
DA9061_IRQ_GPI4,
|
||||
|
||||
DA9061_NUM_IRQ,
|
||||
};
|
||||
|
||||
enum da9062_irqs {
|
||||
/* IRQ A */
|
||||
DA9062_IRQ_ONKEY,
|
||||
DA9062_IRQ_ALARM,
|
||||
DA9062_IRQ_TICK,
|
||||
DA9062_IRQ_WDG_WARN,
|
||||
DA9062_IRQ_SEQ_RDY,
|
||||
/* IRQ B*/
|
||||
DA9062_IRQ_TEMP,
|
||||
DA9062_IRQ_LDO_LIM,
|
||||
DA9062_IRQ_DVC_RDY,
|
||||
DA9062_IRQ_VDD_WARN,
|
||||
/* IRQ C */
|
||||
DA9062_IRQ_GPI0,
|
||||
DA9062_IRQ_GPI1,
|
||||
DA9062_IRQ_GPI2,
|
||||
DA9062_IRQ_GPI3,
|
||||
DA9062_IRQ_GPI4,
|
||||
|
||||
DA9062_NUM_IRQ,
|
||||
};
|
||||
|
||||
struct da9062 {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
struct regmap_irq_chip_data *regmap_irq;
|
||||
enum da9062_compatible_types chip_type;
|
||||
};
|
||||
|
||||
#endif /* __MFD_DA9062_CORE_H__ */
|
||||
@@ -1,95 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Definitions for DA9063 MFD driver
|
||||
*
|
||||
* Copyright 2012 Dialog Semiconductor Ltd.
|
||||
*
|
||||
* Author: Michal Hajduk, Dialog Semiconductor
|
||||
* Author: Krystian Garbaciak, Dialog Semiconductor
|
||||
*/
|
||||
|
||||
#ifndef __MFD_DA9063_CORE_H__
|
||||
#define __MFD_DA9063_CORE_H__
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mfd/da9063/registers.h>
|
||||
|
||||
/* DA9063 modules */
|
||||
#define DA9063_DRVNAME_CORE "da9063-core"
|
||||
#define DA9063_DRVNAME_REGULATORS "da9063-regulators"
|
||||
#define DA9063_DRVNAME_LEDS "da9063-leds"
|
||||
#define DA9063_DRVNAME_WATCHDOG "da9063-watchdog"
|
||||
#define DA9063_DRVNAME_HWMON "da9063-hwmon"
|
||||
#define DA9063_DRVNAME_ONKEY "da9063-onkey"
|
||||
#define DA9063_DRVNAME_RTC "da9063-rtc"
|
||||
#define DA9063_DRVNAME_VIBRATION "da9063-vibration"
|
||||
|
||||
#define PMIC_CHIP_ID_DA9063 0x61
|
||||
|
||||
enum da9063_type {
|
||||
PMIC_TYPE_DA9063 = 0,
|
||||
PMIC_TYPE_DA9063L,
|
||||
};
|
||||
|
||||
enum da9063_variant_codes {
|
||||
PMIC_DA9063_AD = 0x3,
|
||||
PMIC_DA9063_BB = 0x5,
|
||||
PMIC_DA9063_CA = 0x6,
|
||||
PMIC_DA9063_DA = 0x7,
|
||||
PMIC_DA9063_EA = 0x8,
|
||||
};
|
||||
|
||||
/* Interrupts */
|
||||
enum da9063_irqs {
|
||||
DA9063_IRQ_ONKEY = 0,
|
||||
DA9063_IRQ_ALARM,
|
||||
DA9063_IRQ_TICK,
|
||||
DA9063_IRQ_ADC_RDY,
|
||||
DA9063_IRQ_SEQ_RDY,
|
||||
DA9063_IRQ_WAKE,
|
||||
DA9063_IRQ_TEMP,
|
||||
DA9063_IRQ_COMP_1V2,
|
||||
DA9063_IRQ_LDO_LIM,
|
||||
DA9063_IRQ_REG_UVOV,
|
||||
DA9063_IRQ_DVC_RDY,
|
||||
DA9063_IRQ_VDD_MON,
|
||||
DA9063_IRQ_WARN,
|
||||
DA9063_IRQ_GPI0,
|
||||
DA9063_IRQ_GPI1,
|
||||
DA9063_IRQ_GPI2,
|
||||
DA9063_IRQ_GPI3,
|
||||
DA9063_IRQ_GPI4,
|
||||
DA9063_IRQ_GPI5,
|
||||
DA9063_IRQ_GPI6,
|
||||
DA9063_IRQ_GPI7,
|
||||
DA9063_IRQ_GPI8,
|
||||
DA9063_IRQ_GPI9,
|
||||
DA9063_IRQ_GPI10,
|
||||
DA9063_IRQ_GPI11,
|
||||
DA9063_IRQ_GPI12,
|
||||
DA9063_IRQ_GPI13,
|
||||
DA9063_IRQ_GPI14,
|
||||
DA9063_IRQ_GPI15,
|
||||
};
|
||||
|
||||
struct da9063 {
|
||||
/* Device */
|
||||
struct device *dev;
|
||||
enum da9063_type type;
|
||||
unsigned char variant_code;
|
||||
unsigned int flags;
|
||||
bool use_sw_pm;
|
||||
|
||||
/* Control interface */
|
||||
struct regmap *regmap;
|
||||
|
||||
/* Interrupts */
|
||||
int chip_irq;
|
||||
unsigned int irq_base;
|
||||
struct regmap_irq_chip_data *regmap_irq;
|
||||
};
|
||||
|
||||
int da9063_device_init(struct da9063 *da9063, unsigned int irq);
|
||||
int da9063_irq_init(struct da9063 *da9063);
|
||||
|
||||
#endif /* __MFD_DA9063_CORE_H__ */
|
||||
@@ -1,81 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* DA9150 MFD Driver - Core Data
|
||||
*
|
||||
* Copyright (c) 2014 Dialog Semiconductor
|
||||
*
|
||||
* Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
|
||||
*/
|
||||
|
||||
#ifndef __DA9150_CORE_H
|
||||
#define __DA9150_CORE_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
/* I2C address paging */
|
||||
#define DA9150_REG_PAGE_SHIFT 8
|
||||
#define DA9150_REG_PAGE_MASK 0xFF
|
||||
|
||||
/* IRQs */
|
||||
#define DA9150_NUM_IRQ_REGS 4
|
||||
#define DA9150_IRQ_VBUS 0
|
||||
#define DA9150_IRQ_CHG 1
|
||||
#define DA9150_IRQ_TCLASS 2
|
||||
#define DA9150_IRQ_TJUNC 3
|
||||
#define DA9150_IRQ_VFAULT 4
|
||||
#define DA9150_IRQ_CONF 5
|
||||
#define DA9150_IRQ_DAT 6
|
||||
#define DA9150_IRQ_DTYPE 7
|
||||
#define DA9150_IRQ_ID 8
|
||||
#define DA9150_IRQ_ADP 9
|
||||
#define DA9150_IRQ_SESS_END 10
|
||||
#define DA9150_IRQ_SESS_VLD 11
|
||||
#define DA9150_IRQ_FG 12
|
||||
#define DA9150_IRQ_GP 13
|
||||
#define DA9150_IRQ_TBAT 14
|
||||
#define DA9150_IRQ_GPIOA 15
|
||||
#define DA9150_IRQ_GPIOB 16
|
||||
#define DA9150_IRQ_GPIOC 17
|
||||
#define DA9150_IRQ_GPIOD 18
|
||||
#define DA9150_IRQ_GPADC 19
|
||||
#define DA9150_IRQ_WKUP 20
|
||||
|
||||
/* I2C sub-device address */
|
||||
#define DA9150_QIF_I2C_ADDR_LSB 0x5
|
||||
|
||||
struct da9150_fg_pdata {
|
||||
u32 update_interval; /* msecs */
|
||||
u8 warn_soc_lvl; /* % value */
|
||||
u8 crit_soc_lvl; /* % value */
|
||||
};
|
||||
|
||||
struct da9150_pdata {
|
||||
int irq_base;
|
||||
struct da9150_fg_pdata *fg_pdata;
|
||||
};
|
||||
|
||||
struct da9150 {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
struct i2c_client *core_qif;
|
||||
|
||||
struct regmap_irq_chip_data *regmap_irq_data;
|
||||
int irq;
|
||||
int irq_base;
|
||||
};
|
||||
|
||||
/* Device I/O - Query Interface for FG and standard register access */
|
||||
void da9150_read_qif(struct da9150 *da9150, u8 addr, int count, u8 *buf);
|
||||
void da9150_write_qif(struct da9150 *da9150, u8 addr, int count, const u8 *buf);
|
||||
|
||||
u8 da9150_reg_read(struct da9150 *da9150, u16 reg);
|
||||
void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val);
|
||||
void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val);
|
||||
|
||||
void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf);
|
||||
void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf);
|
||||
|
||||
#endif /* __DA9150_CORE_H */
|
||||
@@ -1,210 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* MFD internals for Cirrus Logic Madera codecs
|
||||
*
|
||||
* Copyright (C) 2015-2018 Cirrus Logic
|
||||
*/
|
||||
|
||||
#ifndef MADERA_CORE_H
|
||||
#define MADERA_CORE_H
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mfd/madera/pdata.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
|
||||
enum madera_type {
|
||||
/* 0 is reserved for indicating failure to identify */
|
||||
CS47L35 = 1,
|
||||
CS47L85 = 2,
|
||||
CS47L90 = 3,
|
||||
CS47L91 = 4,
|
||||
CS47L92 = 5,
|
||||
CS47L93 = 6,
|
||||
WM1840 = 7,
|
||||
CS47L15 = 8,
|
||||
CS42L92 = 9,
|
||||
};
|
||||
|
||||
enum {
|
||||
MADERA_MCLK1,
|
||||
MADERA_MCLK2,
|
||||
MADERA_MCLK3,
|
||||
MADERA_NUM_MCLK
|
||||
};
|
||||
|
||||
#define MADERA_MAX_CORE_SUPPLIES 2
|
||||
#define MADERA_MAX_GPIOS 40
|
||||
|
||||
#define CS47L15_NUM_GPIOS 15
|
||||
#define CS47L35_NUM_GPIOS 16
|
||||
#define CS47L85_NUM_GPIOS 40
|
||||
#define CS47L90_NUM_GPIOS 38
|
||||
#define CS47L92_NUM_GPIOS 16
|
||||
|
||||
#define MADERA_MAX_MICBIAS 4
|
||||
|
||||
#define MADERA_MAX_HP_OUTPUT 3
|
||||
|
||||
/* Notifier events */
|
||||
#define MADERA_NOTIFY_VOICE_TRIGGER 0x1
|
||||
#define MADERA_NOTIFY_HPDET 0x2
|
||||
#define MADERA_NOTIFY_MICDET 0x4
|
||||
|
||||
/* GPIO Function Definitions */
|
||||
#define MADERA_GP_FN_ALTERNATE 0x00
|
||||
#define MADERA_GP_FN_GPIO 0x01
|
||||
#define MADERA_GP_FN_DSP_GPIO 0x02
|
||||
#define MADERA_GP_FN_IRQ1 0x03
|
||||
#define MADERA_GP_FN_IRQ2 0x04
|
||||
#define MADERA_GP_FN_FLL1_CLOCK 0x10
|
||||
#define MADERA_GP_FN_FLL2_CLOCK 0x11
|
||||
#define MADERA_GP_FN_FLL3_CLOCK 0x12
|
||||
#define MADERA_GP_FN_FLLAO_CLOCK 0x13
|
||||
#define MADERA_GP_FN_FLL1_LOCK 0x18
|
||||
#define MADERA_GP_FN_FLL2_LOCK 0x19
|
||||
#define MADERA_GP_FN_FLL3_LOCK 0x1A
|
||||
#define MADERA_GP_FN_FLLAO_LOCK 0x1B
|
||||
#define MADERA_GP_FN_OPCLK_OUT 0x40
|
||||
#define MADERA_GP_FN_OPCLK_ASYNC_OUT 0x41
|
||||
#define MADERA_GP_FN_PWM1 0x48
|
||||
#define MADERA_GP_FN_PWM2 0x49
|
||||
#define MADERA_GP_FN_SPDIF_OUT 0x4C
|
||||
#define MADERA_GP_FN_HEADPHONE_DET 0x50
|
||||
#define MADERA_GP_FN_MIC_DET 0x58
|
||||
#define MADERA_GP_FN_DRC1_SIGNAL_DETECT 0x80
|
||||
#define MADERA_GP_FN_DRC2_SIGNAL_DETECT 0x81
|
||||
#define MADERA_GP_FN_ASRC1_IN1_LOCK 0x88
|
||||
#define MADERA_GP_FN_ASRC1_IN2_LOCK 0x89
|
||||
#define MADERA_GP_FN_ASRC2_IN1_LOCK 0x8A
|
||||
#define MADERA_GP_FN_ASRC2_IN2_LOCK 0x8B
|
||||
#define MADERA_GP_FN_DSP_IRQ1 0xA0
|
||||
#define MADERA_GP_FN_DSP_IRQ2 0xA1
|
||||
#define MADERA_GP_FN_DSP_IRQ3 0xA2
|
||||
#define MADERA_GP_FN_DSP_IRQ4 0xA3
|
||||
#define MADERA_GP_FN_DSP_IRQ5 0xA4
|
||||
#define MADERA_GP_FN_DSP_IRQ6 0xA5
|
||||
#define MADERA_GP_FN_DSP_IRQ7 0xA6
|
||||
#define MADERA_GP_FN_DSP_IRQ8 0xA7
|
||||
#define MADERA_GP_FN_DSP_IRQ9 0xA8
|
||||
#define MADERA_GP_FN_DSP_IRQ10 0xA9
|
||||
#define MADERA_GP_FN_DSP_IRQ11 0xAA
|
||||
#define MADERA_GP_FN_DSP_IRQ12 0xAB
|
||||
#define MADERA_GP_FN_DSP_IRQ13 0xAC
|
||||
#define MADERA_GP_FN_DSP_IRQ14 0xAD
|
||||
#define MADERA_GP_FN_DSP_IRQ15 0xAE
|
||||
#define MADERA_GP_FN_DSP_IRQ16 0xAF
|
||||
#define MADERA_GP_FN_HPOUT1L_SC 0xB0
|
||||
#define MADERA_GP_FN_HPOUT1R_SC 0xB1
|
||||
#define MADERA_GP_FN_HPOUT2L_SC 0xB2
|
||||
#define MADERA_GP_FN_HPOUT2R_SC 0xB3
|
||||
#define MADERA_GP_FN_HPOUT3L_SC 0xB4
|
||||
#define MADERA_GP_FN_HPOUT4R_SC 0xB5
|
||||
#define MADERA_GP_FN_SPKOUTL_SC 0xB6
|
||||
#define MADERA_GP_FN_SPKOUTR_SC 0xB7
|
||||
#define MADERA_GP_FN_HPOUT1L_ENA 0xC0
|
||||
#define MADERA_GP_FN_HPOUT1R_ENA 0xC1
|
||||
#define MADERA_GP_FN_HPOUT2L_ENA 0xC2
|
||||
#define MADERA_GP_FN_HPOUT2R_ENA 0xC3
|
||||
#define MADERA_GP_FN_HPOUT3L_ENA 0xC4
|
||||
#define MADERA_GP_FN_HPOUT4R_ENA 0xC5
|
||||
#define MADERA_GP_FN_SPKOUTL_ENA 0xC6
|
||||
#define MADERA_GP_FN_SPKOUTR_ENA 0xC7
|
||||
#define MADERA_GP_FN_HPOUT1L_DIS 0xD0
|
||||
#define MADERA_GP_FN_HPOUT1R_DIS 0xD1
|
||||
#define MADERA_GP_FN_HPOUT2L_DIS 0xD2
|
||||
#define MADERA_GP_FN_HPOUT2R_DIS 0xD3
|
||||
#define MADERA_GP_FN_HPOUT3L_DIS 0xD4
|
||||
#define MADERA_GP_FN_HPOUT4R_DIS 0xD5
|
||||
#define MADERA_GP_FN_SPKOUTL_DIS 0xD6
|
||||
#define MADERA_GP_FN_SPKOUTR_DIS 0xD7
|
||||
#define MADERA_GP_FN_SPK_SHUTDOWN 0xE0
|
||||
#define MADERA_GP_FN_SPK_OVH_SHUTDOWN 0xE1
|
||||
#define MADERA_GP_FN_SPK_OVH_WARN 0xE2
|
||||
#define MADERA_GP_FN_TIMER1_STATUS 0x140
|
||||
#define MADERA_GP_FN_TIMER2_STATUS 0x141
|
||||
#define MADERA_GP_FN_TIMER3_STATUS 0x142
|
||||
#define MADERA_GP_FN_TIMER4_STATUS 0x143
|
||||
#define MADERA_GP_FN_TIMER5_STATUS 0x144
|
||||
#define MADERA_GP_FN_TIMER6_STATUS 0x145
|
||||
#define MADERA_GP_FN_TIMER7_STATUS 0x146
|
||||
#define MADERA_GP_FN_TIMER8_STATUS 0x147
|
||||
#define MADERA_GP_FN_EVENTLOG1_FIFO_STS 0x150
|
||||
#define MADERA_GP_FN_EVENTLOG2_FIFO_STS 0x151
|
||||
#define MADERA_GP_FN_EVENTLOG3_FIFO_STS 0x152
|
||||
#define MADERA_GP_FN_EVENTLOG4_FIFO_STS 0x153
|
||||
#define MADERA_GP_FN_EVENTLOG5_FIFO_STS 0x154
|
||||
#define MADERA_GP_FN_EVENTLOG6_FIFO_STS 0x155
|
||||
#define MADERA_GP_FN_EVENTLOG7_FIFO_STS 0x156
|
||||
#define MADERA_GP_FN_EVENTLOG8_FIFO_STS 0x157
|
||||
|
||||
struct snd_soc_dapm_context;
|
||||
|
||||
/*
|
||||
* struct madera - internal data shared by the set of Madera drivers
|
||||
*
|
||||
* This should not be used by anything except child drivers of the Madera MFD
|
||||
*
|
||||
* @regmap: pointer to the regmap instance for 16-bit registers
|
||||
* @regmap_32bit: pointer to the regmap instance for 32-bit registers
|
||||
* @dev: pointer to the MFD device
|
||||
* @type: type of codec
|
||||
* @rev: silicon revision
|
||||
* @type_name: display name of this codec
|
||||
* @num_core_supplies: number of core supply regulators
|
||||
* @core_supplies: list of core supplies that are always required
|
||||
* @dcvdd: pointer to DCVDD regulator
|
||||
* @internal_dcvdd: true if DCVDD is supplied from the internal LDO1
|
||||
* @pdata: our pdata
|
||||
* @irq_dev: the irqchip child driver device
|
||||
* @irq_data: pointer to irqchip data for the child irqchip driver
|
||||
* @irq: host irq number from SPI or I2C configuration
|
||||
* @mclk: Structure holding clock supplies
|
||||
* @out_clamp: indicates output clamp state for each analogue output
|
||||
* @out_shorted: indicates short circuit state for each analogue output
|
||||
* @hp_ena: bitflags of enable state for the headphone outputs
|
||||
* @num_micbias: number of MICBIAS outputs
|
||||
* @num_childbias: number of child biases for each MICBIAS
|
||||
* @dapm: pointer to codec driver DAPM context
|
||||
* @notifier: notifier for signalling events to ASoC machine driver
|
||||
*/
|
||||
struct madera {
|
||||
struct regmap *regmap;
|
||||
struct regmap *regmap_32bit;
|
||||
|
||||
struct device *dev;
|
||||
|
||||
enum madera_type type;
|
||||
unsigned int rev;
|
||||
const char *type_name;
|
||||
|
||||
int num_core_supplies;
|
||||
struct regulator_bulk_data core_supplies[MADERA_MAX_CORE_SUPPLIES];
|
||||
struct regulator *dcvdd;
|
||||
bool internal_dcvdd;
|
||||
bool reset_errata;
|
||||
|
||||
struct madera_pdata pdata;
|
||||
|
||||
struct device *irq_dev;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
int irq;
|
||||
|
||||
struct clk_bulk_data mclk[MADERA_NUM_MCLK];
|
||||
|
||||
unsigned int num_micbias;
|
||||
unsigned int num_childbias[MADERA_MAX_MICBIAS];
|
||||
|
||||
struct snd_soc_dapm_context *dapm;
|
||||
struct mutex dapm_ptr_lock;
|
||||
unsigned int hp_ena;
|
||||
bool out_clamp[MADERA_MAX_HP_OUTPUT];
|
||||
bool out_shorted[MADERA_MAX_HP_OUTPUT];
|
||||
|
||||
struct blocking_notifier_head notifier;
|
||||
};
|
||||
#endif
|
||||
@@ -1,33 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2016 Chen Zhong <chen.zhong@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6323_CORE_H__
|
||||
#define __MFD_MT6323_CORE_H__
|
||||
|
||||
enum MT6323_IRQ_STATUS_numbers {
|
||||
MT6323_IRQ_STATUS_SPKL_AB = 0,
|
||||
MT6323_IRQ_STATUS_SPKL,
|
||||
MT6323_IRQ_STATUS_BAT_L,
|
||||
MT6323_IRQ_STATUS_BAT_H,
|
||||
MT6323_IRQ_STATUS_WATCHDOG,
|
||||
MT6323_IRQ_STATUS_PWRKEY,
|
||||
MT6323_IRQ_STATUS_THR_L,
|
||||
MT6323_IRQ_STATUS_THR_H,
|
||||
MT6323_IRQ_STATUS_VBATON_UNDET,
|
||||
MT6323_IRQ_STATUS_BVALID_DET,
|
||||
MT6323_IRQ_STATUS_CHRDET,
|
||||
MT6323_IRQ_STATUS_OV,
|
||||
MT6323_IRQ_STATUS_LDO = 16,
|
||||
MT6323_IRQ_STATUS_FCHRKEY,
|
||||
MT6323_IRQ_STATUS_ACCDET,
|
||||
MT6323_IRQ_STATUS_AUDIO,
|
||||
MT6323_IRQ_STATUS_RTC,
|
||||
MT6323_IRQ_STATUS_VPROC,
|
||||
MT6323_IRQ_STATUS_VSYS,
|
||||
MT6323_IRQ_STATUS_VPA,
|
||||
MT6323_IRQ_STATUS_NR,
|
||||
};
|
||||
|
||||
#endif /* __MFD_MT6323_CORE_H__ */
|
||||
@@ -1,53 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2015 MediaTek Inc.
|
||||
* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6328_CORE_H__
|
||||
#define __MFD_MT6328_CORE_H__
|
||||
|
||||
enum mt6328_irq_status_numbers {
|
||||
MT6328_IRQ_STATUS_PWRKEY = 0,
|
||||
MT6328_IRQ_STATUS_HOMEKEY,
|
||||
MT6328_IRQ_STATUS_PWRKEY_R,
|
||||
MT6328_IRQ_STATUS_HOMEKEY_R,
|
||||
MT6328_IRQ_STATUS_THR_H,
|
||||
MT6328_IRQ_STATUS_THR_L,
|
||||
MT6328_IRQ_STATUS_BAT_H,
|
||||
MT6328_IRQ_STATUS_BAT_L,
|
||||
MT6328_IRQ_STATUS_RTC,
|
||||
MT6328_IRQ_STATUS_AUDIO,
|
||||
MT6328_IRQ_STATUS_ACCDET,
|
||||
MT6328_IRQ_STATUS_ACCDET_EINT,
|
||||
MT6328_IRQ_STATUS_ACCDET_NEGV,
|
||||
MT6328_IRQ_STATUS_NI_LBAT_INT,
|
||||
MT6328_IRQ_STATUS_VPROC_OC = 16,
|
||||
MT6328_IRQ_STATUS_VSYS_OC,
|
||||
MT6328_IRQ_STATUS_VLTE_OC,
|
||||
MT6328_IRQ_STATUS_VCORE_OC,
|
||||
MT6328_IRQ_STATUS_VPA_OC,
|
||||
MT6328_IRQ_STATUS_LDO_OC,
|
||||
MT6328_IRQ_STATUS_BAT2_H,
|
||||
MT6328_IRQ_STATUS_BAT2_L,
|
||||
MT6328_IRQ_STATUS_VISMPS0_H,
|
||||
MT6328_IRQ_STATUS_VISMPS0_L,
|
||||
MT6328_IRQ_STATUS_AUXADC_IMP,
|
||||
MT6328_IRQ_STATUS_OV = 32,
|
||||
MT6328_IRQ_STATUS_BVALID_DET,
|
||||
MT6328_IRQ_STATUS_VBATON_HV,
|
||||
MT6328_IRQ_STATUS_VBATON_UNDET,
|
||||
MT6328_IRQ_STATUS_WATCHDOG,
|
||||
MT6328_IRQ_STATUS_PCHR_CM_VDEC,
|
||||
MT6328_IRQ_STATUS_CHRDET,
|
||||
MT6328_IRQ_STATUS_PCHR_CM_VINC,
|
||||
MT6328_IRQ_STATUS_FG_BAT_H,
|
||||
MT6328_IRQ_STATUS_FG_BAT_L,
|
||||
MT6328_IRQ_STATUS_FG_CUR_H,
|
||||
MT6328_IRQ_STATUS_FG_CUR_L,
|
||||
MT6328_IRQ_STATUS_FG_ZCV,
|
||||
MT6328_IRQ_STATUS_SPKL_D,
|
||||
MT6328_IRQ_STATUS_SPKL_AB,
|
||||
};
|
||||
|
||||
#endif /* __MFD_MT6323_CORE_H__ */
|
||||
@@ -1,40 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6331_CORE_H__
|
||||
#define __MFD_MT6331_CORE_H__
|
||||
|
||||
enum mt6331_irq_status_numbers {
|
||||
MT6331_IRQ_STATUS_PWRKEY = 0,
|
||||
MT6331_IRQ_STATUS_HOMEKEY,
|
||||
MT6331_IRQ_STATUS_CHRDET,
|
||||
MT6331_IRQ_STATUS_THR_H,
|
||||
MT6331_IRQ_STATUS_THR_L,
|
||||
MT6331_IRQ_STATUS_BAT_H,
|
||||
MT6331_IRQ_STATUS_BAT_L,
|
||||
MT6331_IRQ_STATUS_RTC,
|
||||
MT6331_IRQ_STATUS_AUDIO,
|
||||
MT6331_IRQ_STATUS_MAD,
|
||||
MT6331_IRQ_STATUS_ACCDET,
|
||||
MT6331_IRQ_STATUS_ACCDET_EINT,
|
||||
MT6331_IRQ_STATUS_ACCDET_NEGV = 12,
|
||||
MT6331_IRQ_STATUS_VDVFS11_OC = 16,
|
||||
MT6331_IRQ_STATUS_VDVFS12_OC,
|
||||
MT6331_IRQ_STATUS_VDVFS13_OC,
|
||||
MT6331_IRQ_STATUS_VDVFS14_OC,
|
||||
MT6331_IRQ_STATUS_GPU_OC,
|
||||
MT6331_IRQ_STATUS_VCORE1_OC,
|
||||
MT6331_IRQ_STATUS_VCORE2_OC,
|
||||
MT6331_IRQ_STATUS_VIO18_OC,
|
||||
MT6331_IRQ_STATUS_LDO_OC,
|
||||
MT6331_IRQ_STATUS_NR,
|
||||
};
|
||||
|
||||
#define MT6331_IRQ_CON0_BASE MT6331_IRQ_STATUS_PWRKEY
|
||||
#define MT6331_IRQ_CON0_BITS (MT6331_IRQ_STATUS_ACCDET_NEGV + 1)
|
||||
#define MT6331_IRQ_CON1_BASE MT6331_IRQ_STATUS_VDVFS11_OC
|
||||
#define MT6331_IRQ_CON1_BITS (MT6331_IRQ_STATUS_LDO_OC - MT6331_IRQ_STATUS_VDFS11_OC + 1)
|
||||
|
||||
#endif /* __MFD_MT6331_CORE_H__ */
|
||||
@@ -1,65 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6332_CORE_H__
|
||||
#define __MFD_MT6332_CORE_H__
|
||||
|
||||
enum mt6332_irq_status_numbers {
|
||||
MT6332_IRQ_STATUS_CHR_COMPLETE = 0,
|
||||
MT6332_IRQ_STATUS_THERMAL_SD,
|
||||
MT6332_IRQ_STATUS_THERMAL_REG_IN,
|
||||
MT6332_IRQ_STATUS_THERMAL_REG_OUT,
|
||||
MT6332_IRQ_STATUS_OTG_OC,
|
||||
MT6332_IRQ_STATUS_CHR_OC,
|
||||
MT6332_IRQ_STATUS_OTG_THERMAL,
|
||||
MT6332_IRQ_STATUS_CHRIN_SHORT,
|
||||
MT6332_IRQ_STATUS_DRVCDT_SHORT,
|
||||
MT6332_IRQ_STATUS_PLUG_IN_FLASH,
|
||||
MT6332_IRQ_STATUS_CHRWDT_FLAG,
|
||||
MT6332_IRQ_STATUS_FLASH_EN_TIMEOUT,
|
||||
MT6332_IRQ_STATUS_FLASH_VLED1_SHORT,
|
||||
MT6332_IRQ_STATUS_FLASH_VLED1_OPEN = 13,
|
||||
MT6332_IRQ_STATUS_OV = 16,
|
||||
MT6332_IRQ_STATUS_BVALID_DET,
|
||||
MT6332_IRQ_STATUS_VBATON_UNDET,
|
||||
MT6332_IRQ_STATUS_CHR_PLUG_IN,
|
||||
MT6332_IRQ_STATUS_CHR_PLUG_OUT,
|
||||
MT6332_IRQ_STATUS_BC11_TIMEOUT,
|
||||
MT6332_IRQ_STATUS_FLASH_VLED2_SHORT,
|
||||
MT6332_IRQ_STATUS_FLASH_VLED2_OPEN = 23,
|
||||
MT6332_IRQ_STATUS_THR_H = 32,
|
||||
MT6332_IRQ_STATUS_THR_L,
|
||||
MT6332_IRQ_STATUS_BAT_H,
|
||||
MT6332_IRQ_STATUS_BAT_L,
|
||||
MT6332_IRQ_STATUS_M3_H,
|
||||
MT6332_IRQ_STATUS_M3_L,
|
||||
MT6332_IRQ_STATUS_FG_BAT_H,
|
||||
MT6332_IRQ_STATUS_FG_BAT_L,
|
||||
MT6332_IRQ_STATUS_FG_CUR_H,
|
||||
MT6332_IRQ_STATUS_FG_CUR_L,
|
||||
MT6332_IRQ_STATUS_SPKL_D,
|
||||
MT6332_IRQ_STATUS_SPKL_AB,
|
||||
MT6332_IRQ_STATUS_BIF,
|
||||
MT6332_IRQ_STATUS_VWLED_OC = 45,
|
||||
MT6332_IRQ_STATUS_VDRAM_OC = 48,
|
||||
MT6332_IRQ_STATUS_VDVFS2_OC,
|
||||
MT6332_IRQ_STATUS_VRF1_OC,
|
||||
MT6332_IRQ_STATUS_VRF2_OC,
|
||||
MT6332_IRQ_STATUS_VPA_OC,
|
||||
MT6332_IRQ_STATUS_VSBST_OC,
|
||||
MT6332_IRQ_STATUS_LDO_OC,
|
||||
MT6332_IRQ_STATUS_NR,
|
||||
};
|
||||
|
||||
#define MT6332_IRQ_CON0_BASE MT6332_IRQ_STATUS_CHR_COMPLETE
|
||||
#define MT6332_IRQ_CON0_BITS (MT6332_IRQ_STATUS_FLASH_VLED1_OPEN + 1)
|
||||
#define MT6332_IRQ_CON1_BASE MT6332_IRQ_STATUS_OV
|
||||
#define MT6332_IRQ_CON1_BITS (MT6332_IRQ_STATUS_FLASH_VLED2_OPEN - MT6332_IRQ_STATUS_OV + 1)
|
||||
#define MT6332_IRQ_CON2_BASE MT6332_IRQ_STATUS_THR_H
|
||||
#define MT6332_IRQ_CON2_BITS (MT6332_IRQ_STATUS_VWLED_OC - MT6332_IRQ_STATUS_THR_H + 1)
|
||||
#define MT6332_IRQ_CON3_BASE MT6332_IRQ_STATUS_VDRAM_OC
|
||||
#define MT6332_IRQ_CON3_BITS (MT6332_IRQ_STATUS_LDO_OC - MT6332_IRQ_STATUS_VDRAM_OC + 1)
|
||||
|
||||
#endif /* __MFD_MT6332_CORE_H__ */
|
||||
@@ -1,119 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2022 BayLibre, SAS
|
||||
* Author: Fabien Parent <fparent@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6357_CORE_H__
|
||||
#define __MFD_MT6357_CORE_H__
|
||||
|
||||
enum mt6357_irq_top_status_shift {
|
||||
MT6357_BUCK_TOP = 0,
|
||||
MT6357_LDO_TOP,
|
||||
MT6357_PSC_TOP,
|
||||
MT6357_SCK_TOP,
|
||||
MT6357_BM_TOP,
|
||||
MT6357_HK_TOP,
|
||||
MT6357_XPP_TOP,
|
||||
MT6357_AUD_TOP,
|
||||
MT6357_MISC_TOP,
|
||||
};
|
||||
|
||||
enum mt6357_irq_numbers {
|
||||
MT6357_IRQ_VPROC_OC = 0,
|
||||
MT6357_IRQ_VCORE_OC,
|
||||
MT6357_IRQ_VMODEM_OC,
|
||||
MT6357_IRQ_VS1_OC,
|
||||
MT6357_IRQ_VPA_OC,
|
||||
MT6357_IRQ_VCORE_PREOC,
|
||||
MT6357_IRQ_VFE28_OC = 16,
|
||||
MT6357_IRQ_VXO22_OC,
|
||||
MT6357_IRQ_VRF18_OC,
|
||||
MT6357_IRQ_VRF12_OC,
|
||||
MT6357_IRQ_VEFUSE_OC,
|
||||
MT6357_IRQ_VCN33_OC,
|
||||
MT6357_IRQ_VCN28_OC,
|
||||
MT6357_IRQ_VCN18_OC,
|
||||
MT6357_IRQ_VCAMA_OC,
|
||||
MT6357_IRQ_VCAMD_OC,
|
||||
MT6357_IRQ_VCAMIO_OC,
|
||||
MT6357_IRQ_VLDO28_OC,
|
||||
MT6357_IRQ_VUSB33_OC,
|
||||
MT6357_IRQ_VAUX18_OC,
|
||||
MT6357_IRQ_VAUD28_OC,
|
||||
MT6357_IRQ_VIO28_OC,
|
||||
MT6357_IRQ_VIO18_OC,
|
||||
MT6357_IRQ_VSRAM_PROC_OC,
|
||||
MT6357_IRQ_VSRAM_OTHERS_OC,
|
||||
MT6357_IRQ_VIBR_OC,
|
||||
MT6357_IRQ_VDRAM_OC,
|
||||
MT6357_IRQ_VMC_OC,
|
||||
MT6357_IRQ_VMCH_OC,
|
||||
MT6357_IRQ_VEMC_OC,
|
||||
MT6357_IRQ_VSIM1_OC,
|
||||
MT6357_IRQ_VSIM2_OC,
|
||||
MT6357_IRQ_PWRKEY = 48,
|
||||
MT6357_IRQ_HOMEKEY,
|
||||
MT6357_IRQ_PWRKEY_R,
|
||||
MT6357_IRQ_HOMEKEY_R,
|
||||
MT6357_IRQ_NI_LBAT_INT,
|
||||
MT6357_IRQ_CHRDET,
|
||||
MT6357_IRQ_CHRDET_EDGE,
|
||||
MT6357_IRQ_VCDT_HV_DET,
|
||||
MT6357_IRQ_WATCHDOG,
|
||||
MT6357_IRQ_VBATON_UNDET,
|
||||
MT6357_IRQ_BVALID_DET,
|
||||
MT6357_IRQ_OV,
|
||||
MT6357_IRQ_RTC = 64,
|
||||
MT6357_IRQ_FG_BAT0_H = 80,
|
||||
MT6357_IRQ_FG_BAT0_L,
|
||||
MT6357_IRQ_FG_CUR_H,
|
||||
MT6357_IRQ_FG_CUR_L,
|
||||
MT6357_IRQ_FG_ZCV,
|
||||
MT6357_IRQ_BATON_LV = 96,
|
||||
MT6357_IRQ_BATON_HT,
|
||||
MT6357_IRQ_BAT_H = 112,
|
||||
MT6357_IRQ_BAT_L,
|
||||
MT6357_IRQ_AUXADC_IMP,
|
||||
MT6357_IRQ_NAG_C_DLTV,
|
||||
MT6357_IRQ_AUDIO = 128,
|
||||
MT6357_IRQ_ACCDET = 133,
|
||||
MT6357_IRQ_ACCDET_EINT0,
|
||||
MT6357_IRQ_ACCDET_EINT1,
|
||||
MT6357_IRQ_SPI_CMD_ALERT = 144,
|
||||
MT6357_IRQ_NR,
|
||||
};
|
||||
|
||||
#define MT6357_IRQ_BUCK_BASE MT6357_IRQ_VPROC_OC
|
||||
#define MT6357_IRQ_LDO_BASE MT6357_IRQ_VFE28_OC
|
||||
#define MT6357_IRQ_PSC_BASE MT6357_IRQ_PWRKEY
|
||||
#define MT6357_IRQ_SCK_BASE MT6357_IRQ_RTC
|
||||
#define MT6357_IRQ_BM_BASE MT6357_IRQ_FG_BAT0_H
|
||||
#define MT6357_IRQ_HK_BASE MT6357_IRQ_BAT_H
|
||||
#define MT6357_IRQ_AUD_BASE MT6357_IRQ_AUDIO
|
||||
#define MT6357_IRQ_MISC_BASE MT6357_IRQ_SPI_CMD_ALERT
|
||||
|
||||
#define MT6357_IRQ_BUCK_BITS (MT6357_IRQ_VCORE_PREOC - MT6357_IRQ_BUCK_BASE + 1)
|
||||
#define MT6357_IRQ_LDO_BITS (MT6357_IRQ_VSIM2_OC - MT6357_IRQ_LDO_BASE + 1)
|
||||
#define MT6357_IRQ_PSC_BITS (MT6357_IRQ_VCDT_HV_DET - MT6357_IRQ_PSC_BASE + 1)
|
||||
#define MT6357_IRQ_SCK_BITS (MT6357_IRQ_RTC - MT6357_IRQ_SCK_BASE + 1)
|
||||
#define MT6357_IRQ_BM_BITS (MT6357_IRQ_BATON_HT - MT6357_IRQ_BM_BASE + 1)
|
||||
#define MT6357_IRQ_HK_BITS (MT6357_IRQ_NAG_C_DLTV - MT6357_IRQ_HK_BASE + 1)
|
||||
#define MT6357_IRQ_AUD_BITS (MT6357_IRQ_ACCDET_EINT1 - MT6357_IRQ_AUD_BASE + 1)
|
||||
#define MT6357_IRQ_MISC_BITS \
|
||||
(MT6357_IRQ_SPI_CMD_ALERT - MT6357_IRQ_MISC_BASE + 1)
|
||||
|
||||
#define MT6357_TOP_GEN(sp) \
|
||||
{ \
|
||||
.hwirq_base = MT6357_IRQ_##sp##_BASE, \
|
||||
.num_int_regs = \
|
||||
((MT6357_IRQ_##sp##_BITS - 1) / \
|
||||
MTK_PMIC_REG_WIDTH) + 1, \
|
||||
.en_reg = MT6357_##sp##_TOP_INT_CON0, \
|
||||
.en_reg_shift = 0x6, \
|
||||
.sta_reg = MT6357_##sp##_TOP_INT_STATUS0, \
|
||||
.sta_reg_shift = 0x2, \
|
||||
.top_offset = MT6357_##sp##_TOP, \
|
||||
}
|
||||
|
||||
#endif /* __MFD_MT6357_CORE_H__ */
|
||||
@@ -1,156 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6358_CORE_H__
|
||||
#define __MFD_MT6358_CORE_H__
|
||||
|
||||
struct irq_top_t {
|
||||
int hwirq_base;
|
||||
unsigned int num_int_regs;
|
||||
unsigned int en_reg;
|
||||
unsigned int en_reg_shift;
|
||||
unsigned int sta_reg;
|
||||
unsigned int sta_reg_shift;
|
||||
unsigned int top_offset;
|
||||
};
|
||||
|
||||
struct pmic_irq_data {
|
||||
unsigned int num_top;
|
||||
unsigned int num_pmic_irqs;
|
||||
unsigned short top_int_status_reg;
|
||||
bool *enable_hwirq;
|
||||
bool *cache_hwirq;
|
||||
const struct irq_top_t *pmic_ints;
|
||||
};
|
||||
|
||||
enum mt6358_irq_top_status_shift {
|
||||
MT6358_BUCK_TOP = 0,
|
||||
MT6358_LDO_TOP,
|
||||
MT6358_PSC_TOP,
|
||||
MT6358_SCK_TOP,
|
||||
MT6358_BM_TOP,
|
||||
MT6358_HK_TOP,
|
||||
MT6358_AUD_TOP,
|
||||
MT6358_MISC_TOP,
|
||||
};
|
||||
|
||||
enum mt6358_irq_numbers {
|
||||
MT6358_IRQ_VPROC11_OC = 0,
|
||||
MT6358_IRQ_VPROC12_OC,
|
||||
MT6358_IRQ_VCORE_OC,
|
||||
MT6358_IRQ_VGPU_OC,
|
||||
MT6358_IRQ_VMODEM_OC,
|
||||
MT6358_IRQ_VDRAM1_OC,
|
||||
MT6358_IRQ_VS1_OC,
|
||||
MT6358_IRQ_VS2_OC,
|
||||
MT6358_IRQ_VPA_OC,
|
||||
MT6358_IRQ_VCORE_PREOC,
|
||||
MT6358_IRQ_VFE28_OC = 16,
|
||||
MT6358_IRQ_VXO22_OC,
|
||||
MT6358_IRQ_VRF18_OC,
|
||||
MT6358_IRQ_VRF12_OC,
|
||||
MT6358_IRQ_VEFUSE_OC,
|
||||
MT6358_IRQ_VCN33_OC,
|
||||
MT6358_IRQ_VCN28_OC,
|
||||
MT6358_IRQ_VCN18_OC,
|
||||
MT6358_IRQ_VCAMA1_OC,
|
||||
MT6358_IRQ_VCAMA2_OC,
|
||||
MT6358_IRQ_VCAMD_OC,
|
||||
MT6358_IRQ_VCAMIO_OC,
|
||||
MT6358_IRQ_VLDO28_OC,
|
||||
MT6358_IRQ_VA12_OC,
|
||||
MT6358_IRQ_VAUX18_OC,
|
||||
MT6358_IRQ_VAUD28_OC,
|
||||
MT6358_IRQ_VIO28_OC,
|
||||
MT6358_IRQ_VIO18_OC,
|
||||
MT6358_IRQ_VSRAM_PROC11_OC,
|
||||
MT6358_IRQ_VSRAM_PROC12_OC,
|
||||
MT6358_IRQ_VSRAM_OTHERS_OC,
|
||||
MT6358_IRQ_VSRAM_GPU_OC,
|
||||
MT6358_IRQ_VDRAM2_OC,
|
||||
MT6358_IRQ_VMC_OC,
|
||||
MT6358_IRQ_VMCH_OC,
|
||||
MT6358_IRQ_VEMC_OC,
|
||||
MT6358_IRQ_VSIM1_OC,
|
||||
MT6358_IRQ_VSIM2_OC,
|
||||
MT6358_IRQ_VIBR_OC,
|
||||
MT6358_IRQ_VUSB_OC,
|
||||
MT6358_IRQ_VBIF28_OC,
|
||||
MT6358_IRQ_PWRKEY = 48,
|
||||
MT6358_IRQ_HOMEKEY,
|
||||
MT6358_IRQ_PWRKEY_R,
|
||||
MT6358_IRQ_HOMEKEY_R,
|
||||
MT6358_IRQ_NI_LBAT_INT,
|
||||
MT6358_IRQ_CHRDET,
|
||||
MT6358_IRQ_CHRDET_EDGE,
|
||||
MT6358_IRQ_VCDT_HV_DET,
|
||||
MT6358_IRQ_RTC = 64,
|
||||
MT6358_IRQ_FG_BAT0_H = 80,
|
||||
MT6358_IRQ_FG_BAT0_L,
|
||||
MT6358_IRQ_FG_CUR_H,
|
||||
MT6358_IRQ_FG_CUR_L,
|
||||
MT6358_IRQ_FG_ZCV,
|
||||
MT6358_IRQ_FG_BAT1_H,
|
||||
MT6358_IRQ_FG_BAT1_L,
|
||||
MT6358_IRQ_FG_N_CHARGE_L,
|
||||
MT6358_IRQ_FG_IAVG_H,
|
||||
MT6358_IRQ_FG_IAVG_L,
|
||||
MT6358_IRQ_FG_TIME_H,
|
||||
MT6358_IRQ_FG_DISCHARGE,
|
||||
MT6358_IRQ_FG_CHARGE,
|
||||
MT6358_IRQ_BATON_LV = 96,
|
||||
MT6358_IRQ_BATON_HT,
|
||||
MT6358_IRQ_BATON_BAT_IN,
|
||||
MT6358_IRQ_BATON_BAT_OUT,
|
||||
MT6358_IRQ_BIF,
|
||||
MT6358_IRQ_BAT_H = 112,
|
||||
MT6358_IRQ_BAT_L,
|
||||
MT6358_IRQ_BAT2_H,
|
||||
MT6358_IRQ_BAT2_L,
|
||||
MT6358_IRQ_BAT_TEMP_H,
|
||||
MT6358_IRQ_BAT_TEMP_L,
|
||||
MT6358_IRQ_AUXADC_IMP,
|
||||
MT6358_IRQ_NAG_C_DLTV,
|
||||
MT6358_IRQ_AUDIO = 128,
|
||||
MT6358_IRQ_ACCDET = 133,
|
||||
MT6358_IRQ_ACCDET_EINT0,
|
||||
MT6358_IRQ_ACCDET_EINT1,
|
||||
MT6358_IRQ_SPI_CMD_ALERT = 144,
|
||||
MT6358_IRQ_NR,
|
||||
};
|
||||
|
||||
#define MT6358_IRQ_BUCK_BASE MT6358_IRQ_VPROC11_OC
|
||||
#define MT6358_IRQ_LDO_BASE MT6358_IRQ_VFE28_OC
|
||||
#define MT6358_IRQ_PSC_BASE MT6358_IRQ_PWRKEY
|
||||
#define MT6358_IRQ_SCK_BASE MT6358_IRQ_RTC
|
||||
#define MT6358_IRQ_BM_BASE MT6358_IRQ_FG_BAT0_H
|
||||
#define MT6358_IRQ_HK_BASE MT6358_IRQ_BAT_H
|
||||
#define MT6358_IRQ_AUD_BASE MT6358_IRQ_AUDIO
|
||||
#define MT6358_IRQ_MISC_BASE MT6358_IRQ_SPI_CMD_ALERT
|
||||
|
||||
#define MT6358_IRQ_BUCK_BITS (MT6358_IRQ_VCORE_PREOC - MT6358_IRQ_BUCK_BASE + 1)
|
||||
#define MT6358_IRQ_LDO_BITS (MT6358_IRQ_VBIF28_OC - MT6358_IRQ_LDO_BASE + 1)
|
||||
#define MT6358_IRQ_PSC_BITS (MT6358_IRQ_VCDT_HV_DET - MT6358_IRQ_PSC_BASE + 1)
|
||||
#define MT6358_IRQ_SCK_BITS (MT6358_IRQ_RTC - MT6358_IRQ_SCK_BASE + 1)
|
||||
#define MT6358_IRQ_BM_BITS (MT6358_IRQ_BIF - MT6358_IRQ_BM_BASE + 1)
|
||||
#define MT6358_IRQ_HK_BITS (MT6358_IRQ_NAG_C_DLTV - MT6358_IRQ_HK_BASE + 1)
|
||||
#define MT6358_IRQ_AUD_BITS (MT6358_IRQ_ACCDET_EINT1 - MT6358_IRQ_AUD_BASE + 1)
|
||||
#define MT6358_IRQ_MISC_BITS \
|
||||
(MT6358_IRQ_SPI_CMD_ALERT - MT6358_IRQ_MISC_BASE + 1)
|
||||
|
||||
#define MT6358_TOP_GEN(sp) \
|
||||
{ \
|
||||
.hwirq_base = MT6358_IRQ_##sp##_BASE, \
|
||||
.num_int_regs = \
|
||||
((MT6358_IRQ_##sp##_BITS - 1) / \
|
||||
MTK_PMIC_REG_WIDTH) + 1, \
|
||||
.en_reg = MT6358_##sp##_TOP_INT_CON0, \
|
||||
.en_reg_shift = 0x6, \
|
||||
.sta_reg = MT6358_##sp##_TOP_INT_STATUS0, \
|
||||
.sta_reg_shift = 0x2, \
|
||||
.top_offset = MT6358_##sp##_TOP, \
|
||||
}
|
||||
|
||||
#endif /* __MFD_MT6358_CORE_H__ */
|
||||
@@ -1,133 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2021 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6359_CORE_H__
|
||||
#define __MFD_MT6359_CORE_H__
|
||||
|
||||
enum mt6359_irq_top_status_shift {
|
||||
MT6359_BUCK_TOP = 0,
|
||||
MT6359_LDO_TOP,
|
||||
MT6359_PSC_TOP,
|
||||
MT6359_SCK_TOP,
|
||||
MT6359_BM_TOP,
|
||||
MT6359_HK_TOP,
|
||||
MT6359_AUD_TOP = 7,
|
||||
MT6359_MISC_TOP,
|
||||
};
|
||||
|
||||
enum mt6359_irq_numbers {
|
||||
MT6359_IRQ_VCORE_OC = 1,
|
||||
MT6359_IRQ_VGPU11_OC,
|
||||
MT6359_IRQ_VGPU12_OC,
|
||||
MT6359_IRQ_VMODEM_OC,
|
||||
MT6359_IRQ_VPROC1_OC,
|
||||
MT6359_IRQ_VPROC2_OC,
|
||||
MT6359_IRQ_VS1_OC,
|
||||
MT6359_IRQ_VS2_OC,
|
||||
MT6359_IRQ_VPA_OC = 9,
|
||||
MT6359_IRQ_VFE28_OC = 16,
|
||||
MT6359_IRQ_VXO22_OC,
|
||||
MT6359_IRQ_VRF18_OC,
|
||||
MT6359_IRQ_VRF12_OC,
|
||||
MT6359_IRQ_VEFUSE_OC,
|
||||
MT6359_IRQ_VCN33_1_OC,
|
||||
MT6359_IRQ_VCN33_2_OC,
|
||||
MT6359_IRQ_VCN13_OC,
|
||||
MT6359_IRQ_VCN18_OC,
|
||||
MT6359_IRQ_VA09_OC,
|
||||
MT6359_IRQ_VCAMIO_OC,
|
||||
MT6359_IRQ_VA12_OC,
|
||||
MT6359_IRQ_VAUX18_OC,
|
||||
MT6359_IRQ_VAUD18_OC,
|
||||
MT6359_IRQ_VIO18_OC,
|
||||
MT6359_IRQ_VSRAM_PROC1_OC,
|
||||
MT6359_IRQ_VSRAM_PROC2_OC,
|
||||
MT6359_IRQ_VSRAM_OTHERS_OC,
|
||||
MT6359_IRQ_VSRAM_MD_OC,
|
||||
MT6359_IRQ_VEMC_OC,
|
||||
MT6359_IRQ_VSIM1_OC,
|
||||
MT6359_IRQ_VSIM2_OC,
|
||||
MT6359_IRQ_VUSB_OC,
|
||||
MT6359_IRQ_VRFCK_OC,
|
||||
MT6359_IRQ_VBBCK_OC,
|
||||
MT6359_IRQ_VBIF28_OC,
|
||||
MT6359_IRQ_VIBR_OC,
|
||||
MT6359_IRQ_VIO28_OC,
|
||||
MT6359_IRQ_VM18_OC,
|
||||
MT6359_IRQ_VUFS_OC = 45,
|
||||
MT6359_IRQ_PWRKEY = 48,
|
||||
MT6359_IRQ_HOMEKEY,
|
||||
MT6359_IRQ_PWRKEY_R,
|
||||
MT6359_IRQ_HOMEKEY_R,
|
||||
MT6359_IRQ_NI_LBAT_INT,
|
||||
MT6359_IRQ_CHRDET_EDGE = 53,
|
||||
MT6359_IRQ_RTC = 64,
|
||||
MT6359_IRQ_FG_BAT_H = 80,
|
||||
MT6359_IRQ_FG_BAT_L,
|
||||
MT6359_IRQ_FG_CUR_H,
|
||||
MT6359_IRQ_FG_CUR_L,
|
||||
MT6359_IRQ_FG_ZCV = 84,
|
||||
MT6359_IRQ_FG_N_CHARGE_L = 87,
|
||||
MT6359_IRQ_FG_IAVG_H,
|
||||
MT6359_IRQ_FG_IAVG_L = 89,
|
||||
MT6359_IRQ_FG_DISCHARGE = 91,
|
||||
MT6359_IRQ_FG_CHARGE,
|
||||
MT6359_IRQ_BATON_LV = 96,
|
||||
MT6359_IRQ_BATON_BAT_IN = 98,
|
||||
MT6359_IRQ_BATON_BAT_OU,
|
||||
MT6359_IRQ_BIF = 100,
|
||||
MT6359_IRQ_BAT_H = 112,
|
||||
MT6359_IRQ_BAT_L,
|
||||
MT6359_IRQ_BAT2_H,
|
||||
MT6359_IRQ_BAT2_L,
|
||||
MT6359_IRQ_BAT_TEMP_H,
|
||||
MT6359_IRQ_BAT_TEMP_L,
|
||||
MT6359_IRQ_THR_H,
|
||||
MT6359_IRQ_THR_L,
|
||||
MT6359_IRQ_AUXADC_IMP,
|
||||
MT6359_IRQ_NAG_C_DLTV = 121,
|
||||
MT6359_IRQ_AUDIO = 128,
|
||||
MT6359_IRQ_ACCDET = 133,
|
||||
MT6359_IRQ_ACCDET_EINT0,
|
||||
MT6359_IRQ_ACCDET_EINT1,
|
||||
MT6359_IRQ_SPI_CMD_ALERT = 144,
|
||||
MT6359_IRQ_NR,
|
||||
};
|
||||
|
||||
#define MT6359_IRQ_BUCK_BASE MT6359_IRQ_VCORE_OC
|
||||
#define MT6359_IRQ_LDO_BASE MT6359_IRQ_VFE28_OC
|
||||
#define MT6359_IRQ_PSC_BASE MT6359_IRQ_PWRKEY
|
||||
#define MT6359_IRQ_SCK_BASE MT6359_IRQ_RTC
|
||||
#define MT6359_IRQ_BM_BASE MT6359_IRQ_FG_BAT_H
|
||||
#define MT6359_IRQ_HK_BASE MT6359_IRQ_BAT_H
|
||||
#define MT6359_IRQ_AUD_BASE MT6359_IRQ_AUDIO
|
||||
#define MT6359_IRQ_MISC_BASE MT6359_IRQ_SPI_CMD_ALERT
|
||||
|
||||
#define MT6359_IRQ_BUCK_BITS (MT6359_IRQ_VPA_OC - MT6359_IRQ_BUCK_BASE + 1)
|
||||
#define MT6359_IRQ_LDO_BITS (MT6359_IRQ_VUFS_OC - MT6359_IRQ_LDO_BASE + 1)
|
||||
#define MT6359_IRQ_PSC_BITS \
|
||||
(MT6359_IRQ_CHRDET_EDGE - MT6359_IRQ_PSC_BASE + 1)
|
||||
#define MT6359_IRQ_SCK_BITS (MT6359_IRQ_RTC - MT6359_IRQ_SCK_BASE + 1)
|
||||
#define MT6359_IRQ_BM_BITS (MT6359_IRQ_BIF - MT6359_IRQ_BM_BASE + 1)
|
||||
#define MT6359_IRQ_HK_BITS (MT6359_IRQ_NAG_C_DLTV - MT6359_IRQ_HK_BASE + 1)
|
||||
#define MT6359_IRQ_AUD_BITS \
|
||||
(MT6359_IRQ_ACCDET_EINT1 - MT6359_IRQ_AUD_BASE + 1)
|
||||
#define MT6359_IRQ_MISC_BITS \
|
||||
(MT6359_IRQ_SPI_CMD_ALERT - MT6359_IRQ_MISC_BASE + 1)
|
||||
|
||||
#define MT6359_TOP_GEN(sp) \
|
||||
{ \
|
||||
.hwirq_base = MT6359_IRQ_##sp##_BASE, \
|
||||
.num_int_regs = \
|
||||
((MT6359_IRQ_##sp##_BITS - 1) / \
|
||||
MTK_PMIC_REG_WIDTH) + 1, \
|
||||
.en_reg = MT6359_##sp##_TOP_INT_CON0, \
|
||||
.en_reg_shift = 0x6, \
|
||||
.sta_reg = MT6359_##sp##_TOP_INT_STATUS0, \
|
||||
.sta_reg_shift = 0x2, \
|
||||
.top_offset = MT6359_##sp##_TOP, \
|
||||
}
|
||||
|
||||
#endif /* __MFD_MT6359_CORE_H__ */
|
||||
@@ -1,81 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Flora Fu, MediaTek
|
||||
*/
|
||||
|
||||
#ifndef __MFD_MT6397_CORE_H__
|
||||
#define __MFD_MT6397_CORE_H__
|
||||
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/notifier.h>
|
||||
|
||||
enum chip_id {
|
||||
MT6323_CHIP_ID = 0x23,
|
||||
MT6328_CHIP_ID = 0x28,
|
||||
MT6331_CHIP_ID = 0x31,
|
||||
MT6332_CHIP_ID = 0x32,
|
||||
MT6357_CHIP_ID = 0x57,
|
||||
MT6358_CHIP_ID = 0x58,
|
||||
MT6359_CHIP_ID = 0x59,
|
||||
MT6366_CHIP_ID = 0x66,
|
||||
MT6391_CHIP_ID = 0x91,
|
||||
MT6397_CHIP_ID = 0x97,
|
||||
};
|
||||
|
||||
enum mt6397_irq_numbers {
|
||||
MT6397_IRQ_SPKL_AB = 0,
|
||||
MT6397_IRQ_SPKR_AB,
|
||||
MT6397_IRQ_SPKL,
|
||||
MT6397_IRQ_SPKR,
|
||||
MT6397_IRQ_BAT_L,
|
||||
MT6397_IRQ_BAT_H,
|
||||
MT6397_IRQ_FG_BAT_L,
|
||||
MT6397_IRQ_FG_BAT_H,
|
||||
MT6397_IRQ_WATCHDOG,
|
||||
MT6397_IRQ_PWRKEY,
|
||||
MT6397_IRQ_THR_L,
|
||||
MT6397_IRQ_THR_H,
|
||||
MT6397_IRQ_VBATON_UNDET,
|
||||
MT6397_IRQ_BVALID_DET,
|
||||
MT6397_IRQ_CHRDET,
|
||||
MT6397_IRQ_OV,
|
||||
MT6397_IRQ_LDO,
|
||||
MT6397_IRQ_HOMEKEY,
|
||||
MT6397_IRQ_ACCDET,
|
||||
MT6397_IRQ_AUDIO,
|
||||
MT6397_IRQ_RTC,
|
||||
MT6397_IRQ_PWRKEY_RSTB,
|
||||
MT6397_IRQ_HDMI_SIFM,
|
||||
MT6397_IRQ_HDMI_CEC,
|
||||
MT6397_IRQ_VCA15,
|
||||
MT6397_IRQ_VSRMCA15,
|
||||
MT6397_IRQ_VCORE,
|
||||
MT6397_IRQ_VGPU,
|
||||
MT6397_IRQ_VIO18,
|
||||
MT6397_IRQ_VPCA7,
|
||||
MT6397_IRQ_VSRMCA7,
|
||||
MT6397_IRQ_VDRM,
|
||||
MT6397_IRQ_NR,
|
||||
};
|
||||
|
||||
struct mt6397_chip {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
struct notifier_block pm_nb;
|
||||
int irq;
|
||||
struct irq_domain *irq_domain;
|
||||
struct mutex irqlock;
|
||||
u16 wake_mask[3];
|
||||
u16 irq_masks_cur[3];
|
||||
u16 irq_masks_cache[3];
|
||||
u16 int_con[3];
|
||||
u16 int_status[3];
|
||||
u16 chip_id;
|
||||
void *irq_data;
|
||||
};
|
||||
|
||||
int mt6358_irq_init(struct mt6397_chip *chip);
|
||||
int mt6397_irq_init(struct mt6397_chip *chip);
|
||||
|
||||
#endif /* __MFD_MT6397_CORE_H__ */
|
||||
@@ -1,144 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_SEC_CORE_H
|
||||
#define __LINUX_MFD_SEC_CORE_H
|
||||
|
||||
/* Macros to represent minimum voltages for LDO/BUCK */
|
||||
#define MIN_3000_MV 3000000
|
||||
#define MIN_2500_MV 2500000
|
||||
#define MIN_2000_MV 2000000
|
||||
#define MIN_1800_MV 1800000
|
||||
#define MIN_1500_MV 1500000
|
||||
#define MIN_1400_MV 1400000
|
||||
#define MIN_1000_MV 1000000
|
||||
|
||||
#define MIN_900_MV 900000
|
||||
#define MIN_850_MV 850000
|
||||
#define MIN_800_MV 800000
|
||||
#define MIN_750_MV 750000
|
||||
#define MIN_650_MV 650000
|
||||
#define MIN_600_MV 600000
|
||||
#define MIN_500_MV 500000
|
||||
|
||||
/* Ramp delay in uV/us */
|
||||
#define RAMP_DELAY_12_MVUS 12000
|
||||
|
||||
/* Macros to represent steps for LDO/BUCK */
|
||||
#define STEP_50_MV 50000
|
||||
#define STEP_25_MV 25000
|
||||
#define STEP_12_5_MV 12500
|
||||
#define STEP_6_25_MV 6250
|
||||
|
||||
struct gpio_desc;
|
||||
|
||||
enum sec_device_type {
|
||||
S5M8767X,
|
||||
S2DOS05,
|
||||
S2MPA01,
|
||||
S2MPG10,
|
||||
S2MPG11,
|
||||
S2MPS11X,
|
||||
S2MPS13X,
|
||||
S2MPS14X,
|
||||
S2MPS15X,
|
||||
S2MPU02,
|
||||
S2MPU05,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sec_pmic_dev - s2m/s5m master device for sub-drivers
|
||||
* @dev: Master device of the chip
|
||||
* @pdata: Platform data populated with data from DTS
|
||||
* or board files
|
||||
* @regmap_pmic: Regmap associated with PMIC's I2C address
|
||||
* @i2c: I2C client of the main driver
|
||||
* @device_type: Type of device, matches enum sec_device_type
|
||||
* @irq_base: Base IRQ number for device, required for IRQs
|
||||
* @irq: Generic IRQ number for device
|
||||
* @irq_data: Runtime data structure for IRQ controller
|
||||
* @wakeup: Whether or not this is a wakeup device
|
||||
*/
|
||||
struct sec_pmic_dev {
|
||||
struct device *dev;
|
||||
struct sec_platform_data *pdata;
|
||||
struct regmap *regmap_pmic;
|
||||
struct i2c_client *i2c;
|
||||
|
||||
int device_type;
|
||||
int irq;
|
||||
};
|
||||
|
||||
struct sec_platform_data {
|
||||
struct sec_regulator_data *regulators;
|
||||
struct sec_opmode_data *opmode;
|
||||
int num_regulators;
|
||||
|
||||
int buck_gpios[3];
|
||||
int buck_ds[3];
|
||||
unsigned int buck2_voltage[8];
|
||||
bool buck2_gpiodvs;
|
||||
unsigned int buck3_voltage[8];
|
||||
bool buck3_gpiodvs;
|
||||
unsigned int buck4_voltage[8];
|
||||
bool buck4_gpiodvs;
|
||||
|
||||
int buck_default_idx;
|
||||
int buck_ramp_delay;
|
||||
|
||||
bool buck2_ramp_enable;
|
||||
bool buck3_ramp_enable;
|
||||
bool buck4_ramp_enable;
|
||||
|
||||
int buck2_init;
|
||||
int buck3_init;
|
||||
int buck4_init;
|
||||
/* Whether or not manually set PWRHOLD to low during shutdown. */
|
||||
bool manual_poweroff;
|
||||
/* Disable the WRSTBI (buck voltage warm reset) when probing? */
|
||||
bool disable_wrstbi;
|
||||
};
|
||||
|
||||
/**
|
||||
* sec_regulator_data - regulator data
|
||||
* @id: regulator id
|
||||
* @initdata: regulator init data (contraints, supplies, ...)
|
||||
*/
|
||||
struct sec_regulator_data {
|
||||
int id;
|
||||
struct regulator_init_data *initdata;
|
||||
struct device_node *reg_node;
|
||||
struct gpio_desc *ext_control_gpiod;
|
||||
};
|
||||
|
||||
/*
|
||||
* sec_opmode_data - regulator operation mode data
|
||||
* @id: regulator id
|
||||
* @mode: regulator operation mode
|
||||
*/
|
||||
struct sec_opmode_data {
|
||||
int id;
|
||||
unsigned int mode;
|
||||
};
|
||||
|
||||
/*
|
||||
* samsung regulator operation mode
|
||||
* SEC_OPMODE_OFF Regulator always OFF
|
||||
* SEC_OPMODE_ON Regulator always ON
|
||||
* SEC_OPMODE_LOWPOWER Regulator is on in low-power mode
|
||||
* SEC_OPMODE_SUSPEND Regulator is changed by PWREN pin
|
||||
* If PWREN is high, regulator is on
|
||||
* If PWREN is low, regulator is off
|
||||
*/
|
||||
|
||||
enum sec_opmode {
|
||||
SEC_OPMODE_OFF,
|
||||
SEC_OPMODE_ON,
|
||||
SEC_OPMODE_LOWPOWER,
|
||||
SEC_OPMODE_SUSPEND,
|
||||
};
|
||||
|
||||
#endif /* __LINUX_MFD_SEC_CORE_H */
|
||||
@@ -1,431 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* include/linux/mfd/wm831x/core.h -- Core interface for WM831x
|
||||
*
|
||||
* Copyright 2009 Wolfson Microelectronics PLC.
|
||||
*
|
||||
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
*/
|
||||
|
||||
#ifndef __MFD_WM831X_CORE_H__
|
||||
#define __MFD_WM831X_CORE_H__
|
||||
|
||||
#include <linux/completion.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/mfd/wm831x/auxadc.h>
|
||||
#include <linux/mfd/wm831x/pdata.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
/*
|
||||
* Register values.
|
||||
*/
|
||||
#define WM831X_RESET_ID 0x00
|
||||
#define WM831X_REVISION 0x01
|
||||
#define WM831X_PARENT_ID 0x4000
|
||||
#define WM831X_SYSVDD_CONTROL 0x4001
|
||||
#define WM831X_THERMAL_MONITORING 0x4002
|
||||
#define WM831X_POWER_STATE 0x4003
|
||||
#define WM831X_WATCHDOG 0x4004
|
||||
#define WM831X_ON_PIN_CONTROL 0x4005
|
||||
#define WM831X_RESET_CONTROL 0x4006
|
||||
#define WM831X_CONTROL_INTERFACE 0x4007
|
||||
#define WM831X_SECURITY_KEY 0x4008
|
||||
#define WM831X_SOFTWARE_SCRATCH 0x4009
|
||||
#define WM831X_OTP_CONTROL 0x400A
|
||||
#define WM831X_GPIO_LEVEL 0x400C
|
||||
#define WM831X_SYSTEM_STATUS 0x400D
|
||||
#define WM831X_ON_SOURCE 0x400E
|
||||
#define WM831X_OFF_SOURCE 0x400F
|
||||
#define WM831X_SYSTEM_INTERRUPTS 0x4010
|
||||
#define WM831X_INTERRUPT_STATUS_1 0x4011
|
||||
#define WM831X_INTERRUPT_STATUS_2 0x4012
|
||||
#define WM831X_INTERRUPT_STATUS_3 0x4013
|
||||
#define WM831X_INTERRUPT_STATUS_4 0x4014
|
||||
#define WM831X_INTERRUPT_STATUS_5 0x4015
|
||||
#define WM831X_IRQ_CONFIG 0x4017
|
||||
#define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
|
||||
#define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
|
||||
#define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
|
||||
#define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
|
||||
#define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
|
||||
#define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
|
||||
#define WM831X_RTC_WRITE_COUNTER 0x4020
|
||||
#define WM831X_RTC_TIME_1 0x4021
|
||||
#define WM831X_RTC_TIME_2 0x4022
|
||||
#define WM831X_RTC_ALARM_1 0x4023
|
||||
#define WM831X_RTC_ALARM_2 0x4024
|
||||
#define WM831X_RTC_CONTROL 0x4025
|
||||
#define WM831X_RTC_TRIM 0x4026
|
||||
#define WM831X_TOUCH_CONTROL_1 0x4028
|
||||
#define WM831X_TOUCH_CONTROL_2 0x4029
|
||||
#define WM831X_TOUCH_DATA_X 0x402A
|
||||
#define WM831X_TOUCH_DATA_Y 0x402B
|
||||
#define WM831X_TOUCH_DATA_Z 0x402C
|
||||
#define WM831X_AUXADC_DATA 0x402D
|
||||
#define WM831X_AUXADC_CONTROL 0x402E
|
||||
#define WM831X_AUXADC_SOURCE 0x402F
|
||||
#define WM831X_COMPARATOR_CONTROL 0x4030
|
||||
#define WM831X_COMPARATOR_1 0x4031
|
||||
#define WM831X_COMPARATOR_2 0x4032
|
||||
#define WM831X_COMPARATOR_3 0x4033
|
||||
#define WM831X_COMPARATOR_4 0x4034
|
||||
#define WM831X_GPIO1_CONTROL 0x4038
|
||||
#define WM831X_GPIO2_CONTROL 0x4039
|
||||
#define WM831X_GPIO3_CONTROL 0x403A
|
||||
#define WM831X_GPIO4_CONTROL 0x403B
|
||||
#define WM831X_GPIO5_CONTROL 0x403C
|
||||
#define WM831X_GPIO6_CONTROL 0x403D
|
||||
#define WM831X_GPIO7_CONTROL 0x403E
|
||||
#define WM831X_GPIO8_CONTROL 0x403F
|
||||
#define WM831X_GPIO9_CONTROL 0x4040
|
||||
#define WM831X_GPIO10_CONTROL 0x4041
|
||||
#define WM831X_GPIO11_CONTROL 0x4042
|
||||
#define WM831X_GPIO12_CONTROL 0x4043
|
||||
#define WM831X_GPIO13_CONTROL 0x4044
|
||||
#define WM831X_GPIO14_CONTROL 0x4045
|
||||
#define WM831X_GPIO15_CONTROL 0x4046
|
||||
#define WM831X_GPIO16_CONTROL 0x4047
|
||||
#define WM831X_CHARGER_CONTROL_1 0x4048
|
||||
#define WM831X_CHARGER_CONTROL_2 0x4049
|
||||
#define WM831X_CHARGER_STATUS 0x404A
|
||||
#define WM831X_BACKUP_CHARGER_CONTROL 0x404B
|
||||
#define WM831X_STATUS_LED_1 0x404C
|
||||
#define WM831X_STATUS_LED_2 0x404D
|
||||
#define WM831X_CURRENT_SINK_1 0x404E
|
||||
#define WM831X_CURRENT_SINK_2 0x404F
|
||||
#define WM831X_DCDC_ENABLE 0x4050
|
||||
#define WM831X_LDO_ENABLE 0x4051
|
||||
#define WM831X_DCDC_STATUS 0x4052
|
||||
#define WM831X_LDO_STATUS 0x4053
|
||||
#define WM831X_DCDC_UV_STATUS 0x4054
|
||||
#define WM831X_LDO_UV_STATUS 0x4055
|
||||
#define WM831X_DC1_CONTROL_1 0x4056
|
||||
#define WM831X_DC1_CONTROL_2 0x4057
|
||||
#define WM831X_DC1_ON_CONFIG 0x4058
|
||||
#define WM831X_DC1_SLEEP_CONTROL 0x4059
|
||||
#define WM831X_DC1_DVS_CONTROL 0x405A
|
||||
#define WM831X_DC2_CONTROL_1 0x405B
|
||||
#define WM831X_DC2_CONTROL_2 0x405C
|
||||
#define WM831X_DC2_ON_CONFIG 0x405D
|
||||
#define WM831X_DC2_SLEEP_CONTROL 0x405E
|
||||
#define WM831X_DC2_DVS_CONTROL 0x405F
|
||||
#define WM831X_DC3_CONTROL_1 0x4060
|
||||
#define WM831X_DC3_CONTROL_2 0x4061
|
||||
#define WM831X_DC3_ON_CONFIG 0x4062
|
||||
#define WM831X_DC3_SLEEP_CONTROL 0x4063
|
||||
#define WM831X_DC4_CONTROL 0x4064
|
||||
#define WM831X_DC4_SLEEP_CONTROL 0x4065
|
||||
#define WM832X_DC4_SLEEP_CONTROL 0x4067
|
||||
#define WM831X_EPE1_CONTROL 0x4066
|
||||
#define WM831X_EPE2_CONTROL 0x4067
|
||||
#define WM831X_LDO1_CONTROL 0x4068
|
||||
#define WM831X_LDO1_ON_CONTROL 0x4069
|
||||
#define WM831X_LDO1_SLEEP_CONTROL 0x406A
|
||||
#define WM831X_LDO2_CONTROL 0x406B
|
||||
#define WM831X_LDO2_ON_CONTROL 0x406C
|
||||
#define WM831X_LDO2_SLEEP_CONTROL 0x406D
|
||||
#define WM831X_LDO3_CONTROL 0x406E
|
||||
#define WM831X_LDO3_ON_CONTROL 0x406F
|
||||
#define WM831X_LDO3_SLEEP_CONTROL 0x4070
|
||||
#define WM831X_LDO4_CONTROL 0x4071
|
||||
#define WM831X_LDO4_ON_CONTROL 0x4072
|
||||
#define WM831X_LDO4_SLEEP_CONTROL 0x4073
|
||||
#define WM831X_LDO5_CONTROL 0x4074
|
||||
#define WM831X_LDO5_ON_CONTROL 0x4075
|
||||
#define WM831X_LDO5_SLEEP_CONTROL 0x4076
|
||||
#define WM831X_LDO6_CONTROL 0x4077
|
||||
#define WM831X_LDO6_ON_CONTROL 0x4078
|
||||
#define WM831X_LDO6_SLEEP_CONTROL 0x4079
|
||||
#define WM831X_LDO7_CONTROL 0x407A
|
||||
#define WM831X_LDO7_ON_CONTROL 0x407B
|
||||
#define WM831X_LDO7_SLEEP_CONTROL 0x407C
|
||||
#define WM831X_LDO8_CONTROL 0x407D
|
||||
#define WM831X_LDO8_ON_CONTROL 0x407E
|
||||
#define WM831X_LDO8_SLEEP_CONTROL 0x407F
|
||||
#define WM831X_LDO9_CONTROL 0x4080
|
||||
#define WM831X_LDO9_ON_CONTROL 0x4081
|
||||
#define WM831X_LDO9_SLEEP_CONTROL 0x4082
|
||||
#define WM831X_LDO10_CONTROL 0x4083
|
||||
#define WM831X_LDO10_ON_CONTROL 0x4084
|
||||
#define WM831X_LDO10_SLEEP_CONTROL 0x4085
|
||||
#define WM831X_LDO11_ON_CONTROL 0x4087
|
||||
#define WM831X_LDO11_SLEEP_CONTROL 0x4088
|
||||
#define WM831X_POWER_GOOD_SOURCE_1 0x408E
|
||||
#define WM831X_POWER_GOOD_SOURCE_2 0x408F
|
||||
#define WM831X_CLOCK_CONTROL_1 0x4090
|
||||
#define WM831X_CLOCK_CONTROL_2 0x4091
|
||||
#define WM831X_FLL_CONTROL_1 0x4092
|
||||
#define WM831X_FLL_CONTROL_2 0x4093
|
||||
#define WM831X_FLL_CONTROL_3 0x4094
|
||||
#define WM831X_FLL_CONTROL_4 0x4095
|
||||
#define WM831X_FLL_CONTROL_5 0x4096
|
||||
#define WM831X_UNIQUE_ID_1 0x7800
|
||||
#define WM831X_UNIQUE_ID_2 0x7801
|
||||
#define WM831X_UNIQUE_ID_3 0x7802
|
||||
#define WM831X_UNIQUE_ID_4 0x7803
|
||||
#define WM831X_UNIQUE_ID_5 0x7804
|
||||
#define WM831X_UNIQUE_ID_6 0x7805
|
||||
#define WM831X_UNIQUE_ID_7 0x7806
|
||||
#define WM831X_UNIQUE_ID_8 0x7807
|
||||
#define WM831X_FACTORY_OTP_ID 0x7808
|
||||
#define WM831X_FACTORY_OTP_1 0x7809
|
||||
#define WM831X_FACTORY_OTP_2 0x780A
|
||||
#define WM831X_FACTORY_OTP_3 0x780B
|
||||
#define WM831X_FACTORY_OTP_4 0x780C
|
||||
#define WM831X_FACTORY_OTP_5 0x780D
|
||||
#define WM831X_CUSTOMER_OTP_ID 0x7810
|
||||
#define WM831X_DC1_OTP_CONTROL 0x7811
|
||||
#define WM831X_DC2_OTP_CONTROL 0x7812
|
||||
#define WM831X_DC3_OTP_CONTROL 0x7813
|
||||
#define WM831X_LDO1_2_OTP_CONTROL 0x7814
|
||||
#define WM831X_LDO3_4_OTP_CONTROL 0x7815
|
||||
#define WM831X_LDO5_6_OTP_CONTROL 0x7816
|
||||
#define WM831X_LDO7_8_OTP_CONTROL 0x7817
|
||||
#define WM831X_LDO9_10_OTP_CONTROL 0x7818
|
||||
#define WM831X_LDO11_EPE_CONTROL 0x7819
|
||||
#define WM831X_GPIO1_OTP_CONTROL 0x781A
|
||||
#define WM831X_GPIO2_OTP_CONTROL 0x781B
|
||||
#define WM831X_GPIO3_OTP_CONTROL 0x781C
|
||||
#define WM831X_GPIO4_OTP_CONTROL 0x781D
|
||||
#define WM831X_GPIO5_OTP_CONTROL 0x781E
|
||||
#define WM831X_GPIO6_OTP_CONTROL 0x781F
|
||||
#define WM831X_DBE_CHECK_DATA 0x7827
|
||||
|
||||
/*
|
||||
* R0 (0x00) - Reset ID
|
||||
*/
|
||||
#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
|
||||
#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
|
||||
#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
|
||||
|
||||
/*
|
||||
* R1 (0x01) - Revision
|
||||
*/
|
||||
#define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */
|
||||
#define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */
|
||||
#define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */
|
||||
#define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */
|
||||
#define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */
|
||||
#define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */
|
||||
|
||||
/*
|
||||
* R16384 (0x4000) - Parent ID
|
||||
*/
|
||||
#define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */
|
||||
#define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */
|
||||
#define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */
|
||||
|
||||
/*
|
||||
* R16389 (0x4005) - ON Pin Control
|
||||
*/
|
||||
#define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */
|
||||
#define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */
|
||||
#define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */
|
||||
#define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */
|
||||
#define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */
|
||||
#define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */
|
||||
#define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */
|
||||
#define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */
|
||||
#define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */
|
||||
#define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */
|
||||
#define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */
|
||||
#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
|
||||
#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
|
||||
|
||||
/*
|
||||
* R16528 (0x4090) - Clock Control 1
|
||||
*/
|
||||
#define WM831X_CLKOUT_ENA 0x8000 /* CLKOUT_ENA */
|
||||
#define WM831X_CLKOUT_ENA_MASK 0x8000 /* CLKOUT_ENA */
|
||||
#define WM831X_CLKOUT_ENA_SHIFT 15 /* CLKOUT_ENA */
|
||||
#define WM831X_CLKOUT_ENA_WIDTH 1 /* CLKOUT_ENA */
|
||||
#define WM831X_CLKOUT_OD 0x2000 /* CLKOUT_OD */
|
||||
#define WM831X_CLKOUT_OD_MASK 0x2000 /* CLKOUT_OD */
|
||||
#define WM831X_CLKOUT_OD_SHIFT 13 /* CLKOUT_OD */
|
||||
#define WM831X_CLKOUT_OD_WIDTH 1 /* CLKOUT_OD */
|
||||
#define WM831X_CLKOUT_SLOT_MASK 0x0700 /* CLKOUT_SLOT - [10:8] */
|
||||
#define WM831X_CLKOUT_SLOT_SHIFT 8 /* CLKOUT_SLOT - [10:8] */
|
||||
#define WM831X_CLKOUT_SLOT_WIDTH 3 /* CLKOUT_SLOT - [10:8] */
|
||||
#define WM831X_CLKOUT_SLPSLOT_MASK 0x0070 /* CLKOUT_SLPSLOT - [6:4] */
|
||||
#define WM831X_CLKOUT_SLPSLOT_SHIFT 4 /* CLKOUT_SLPSLOT - [6:4] */
|
||||
#define WM831X_CLKOUT_SLPSLOT_WIDTH 3 /* CLKOUT_SLPSLOT - [6:4] */
|
||||
#define WM831X_CLKOUT_SRC 0x0001 /* CLKOUT_SRC */
|
||||
#define WM831X_CLKOUT_SRC_MASK 0x0001 /* CLKOUT_SRC */
|
||||
#define WM831X_CLKOUT_SRC_SHIFT 0 /* CLKOUT_SRC */
|
||||
#define WM831X_CLKOUT_SRC_WIDTH 1 /* CLKOUT_SRC */
|
||||
|
||||
/*
|
||||
* R16529 (0x4091) - Clock Control 2
|
||||
*/
|
||||
#define WM831X_XTAL_INH 0x8000 /* XTAL_INH */
|
||||
#define WM831X_XTAL_INH_MASK 0x8000 /* XTAL_INH */
|
||||
#define WM831X_XTAL_INH_SHIFT 15 /* XTAL_INH */
|
||||
#define WM831X_XTAL_INH_WIDTH 1 /* XTAL_INH */
|
||||
#define WM831X_XTAL_ENA 0x2000 /* XTAL_ENA */
|
||||
#define WM831X_XTAL_ENA_MASK 0x2000 /* XTAL_ENA */
|
||||
#define WM831X_XTAL_ENA_SHIFT 13 /* XTAL_ENA */
|
||||
#define WM831X_XTAL_ENA_WIDTH 1 /* XTAL_ENA */
|
||||
#define WM831X_XTAL_BKUPENA 0x1000 /* XTAL_BKUPENA */
|
||||
#define WM831X_XTAL_BKUPENA_MASK 0x1000 /* XTAL_BKUPENA */
|
||||
#define WM831X_XTAL_BKUPENA_SHIFT 12 /* XTAL_BKUPENA */
|
||||
#define WM831X_XTAL_BKUPENA_WIDTH 1 /* XTAL_BKUPENA */
|
||||
#define WM831X_FLL_AUTO 0x0080 /* FLL_AUTO */
|
||||
#define WM831X_FLL_AUTO_MASK 0x0080 /* FLL_AUTO */
|
||||
#define WM831X_FLL_AUTO_SHIFT 7 /* FLL_AUTO */
|
||||
#define WM831X_FLL_AUTO_WIDTH 1 /* FLL_AUTO */
|
||||
#define WM831X_FLL_AUTO_FREQ_MASK 0x0007 /* FLL_AUTO_FREQ - [2:0] */
|
||||
#define WM831X_FLL_AUTO_FREQ_SHIFT 0 /* FLL_AUTO_FREQ - [2:0] */
|
||||
#define WM831X_FLL_AUTO_FREQ_WIDTH 3 /* FLL_AUTO_FREQ - [2:0] */
|
||||
|
||||
/*
|
||||
* R16530 (0x4092) - FLL Control 1
|
||||
*/
|
||||
#define WM831X_FLL_FRAC 0x0004 /* FLL_FRAC */
|
||||
#define WM831X_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
|
||||
#define WM831X_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
|
||||
#define WM831X_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
|
||||
#define WM831X_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
|
||||
#define WM831X_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
|
||||
#define WM831X_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
|
||||
#define WM831X_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
|
||||
#define WM831X_FLL_ENA 0x0001 /* FLL_ENA */
|
||||
#define WM831X_FLL_ENA_MASK 0x0001 /* FLL_ENA */
|
||||
#define WM831X_FLL_ENA_SHIFT 0 /* FLL_ENA */
|
||||
#define WM831X_FLL_ENA_WIDTH 1 /* FLL_ENA */
|
||||
|
||||
/*
|
||||
* R16531 (0x4093) - FLL Control 2
|
||||
*/
|
||||
#define WM831X_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
|
||||
#define WM831X_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
|
||||
#define WM831X_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
|
||||
#define WM831X_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
|
||||
#define WM831X_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
|
||||
#define WM831X_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
|
||||
#define WM831X_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
|
||||
#define WM831X_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
|
||||
#define WM831X_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
|
||||
|
||||
/*
|
||||
* R16532 (0x4094) - FLL Control 3
|
||||
*/
|
||||
#define WM831X_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
|
||||
#define WM831X_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
|
||||
#define WM831X_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
|
||||
|
||||
/*
|
||||
* R16533 (0x4095) - FLL Control 4
|
||||
*/
|
||||
#define WM831X_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
|
||||
#define WM831X_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
|
||||
#define WM831X_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
|
||||
#define WM831X_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
|
||||
#define WM831X_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
|
||||
#define WM831X_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
|
||||
|
||||
/*
|
||||
* R16534 (0x4096) - FLL Control 5
|
||||
*/
|
||||
#define WM831X_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
|
||||
#define WM831X_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
|
||||
#define WM831X_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
|
||||
#define WM831X_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
|
||||
#define WM831X_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
|
||||
#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
|
||||
|
||||
struct regulator_dev;
|
||||
struct irq_domain;
|
||||
|
||||
#define WM831X_NUM_IRQ_REGS 5
|
||||
#define WM831X_NUM_GPIO_REGS 16
|
||||
|
||||
enum wm831x_parent {
|
||||
WM8310 = 0x8310,
|
||||
WM8311 = 0x8311,
|
||||
WM8312 = 0x8312,
|
||||
WM8320 = 0x8320,
|
||||
WM8321 = 0x8321,
|
||||
WM8325 = 0x8325,
|
||||
WM8326 = 0x8326,
|
||||
};
|
||||
|
||||
struct wm831x;
|
||||
|
||||
typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x,
|
||||
enum wm831x_auxadc input);
|
||||
|
||||
struct wm831x {
|
||||
struct mutex io_lock;
|
||||
|
||||
struct device *dev;
|
||||
|
||||
struct regmap *regmap;
|
||||
|
||||
struct wm831x_pdata pdata;
|
||||
enum wm831x_parent type;
|
||||
|
||||
int irq; /* Our chip IRQ */
|
||||
struct mutex irq_lock;
|
||||
struct irq_domain *irq_domain;
|
||||
int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
|
||||
int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
|
||||
|
||||
bool soft_shutdown;
|
||||
|
||||
/* Chip revision based flags */
|
||||
unsigned has_gpio_ena:1; /* Has GPIO enable bit */
|
||||
unsigned has_cs_sts:1; /* Has current sink status bit */
|
||||
unsigned charger_irq_wake:1; /* Are charger IRQs a wake source? */
|
||||
|
||||
int num_gpio;
|
||||
|
||||
/* Used by the interrupt controller code to post writes */
|
||||
int gpio_update[WM831X_NUM_GPIO_REGS];
|
||||
bool gpio_level_high[WM831X_NUM_GPIO_REGS];
|
||||
bool gpio_level_low[WM831X_NUM_GPIO_REGS];
|
||||
|
||||
struct mutex auxadc_lock;
|
||||
struct list_head auxadc_pending;
|
||||
u16 auxadc_active;
|
||||
wm831x_auxadc_read_fn auxadc_read;
|
||||
|
||||
/* The WM831x has a security key blocking access to certain
|
||||
* registers. The mutex is taken by the accessors for locking
|
||||
* and unlocking the security key, locked is used to fail
|
||||
* writes if the lock is held.
|
||||
*/
|
||||
struct mutex key_lock;
|
||||
unsigned int locked:1;
|
||||
};
|
||||
|
||||
/* Device I/O API */
|
||||
int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
|
||||
int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
|
||||
unsigned short val);
|
||||
void wm831x_reg_lock(struct wm831x *wm831x);
|
||||
int wm831x_reg_unlock(struct wm831x *wm831x);
|
||||
int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
|
||||
unsigned short mask, unsigned short val);
|
||||
int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
|
||||
int count, u16 *buf);
|
||||
|
||||
int wm831x_device_init(struct wm831x *wm831x, int irq);
|
||||
int wm831x_device_suspend(struct wm831x *wm831x);
|
||||
void wm831x_device_shutdown(struct wm831x *wm831x);
|
||||
int wm831x_irq_init(struct wm831x *wm831x, int irq);
|
||||
void wm831x_irq_exit(struct wm831x *wm831x);
|
||||
void wm831x_auxadc_init(struct wm831x *wm831x);
|
||||
|
||||
static inline int wm831x_irq(struct wm831x *wm831x, int irq)
|
||||
{
|
||||
return irq_create_mapping(wm831x->irq_domain, irq);
|
||||
}
|
||||
|
||||
extern struct regmap_config wm831x_regmap_config;
|
||||
|
||||
extern const struct of_device_id wm831x_of_match[];
|
||||
|
||||
#endif
|
||||
@@ -1,692 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* core.h -- Core Driver for Wolfson WM8350 PMIC
|
||||
*
|
||||
* Copyright 2007 Wolfson Microelectronics PLC
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_WM8350_CORE_H_
|
||||
#define __LINUX_MFD_WM8350_CORE_H_
|
||||
|
||||
#include <linux/completion.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <linux/mfd/wm8350/audio.h>
|
||||
#include <linux/mfd/wm8350/gpio.h>
|
||||
#include <linux/mfd/wm8350/pmic.h>
|
||||
#include <linux/mfd/wm8350/rtc.h>
|
||||
#include <linux/mfd/wm8350/supply.h>
|
||||
#include <linux/mfd/wm8350/wdt.h>
|
||||
|
||||
struct device;
|
||||
struct platform_device;
|
||||
|
||||
/*
|
||||
* Register values.
|
||||
*/
|
||||
#define WM8350_RESET_ID 0x00
|
||||
#define WM8350_ID 0x01
|
||||
#define WM8350_REVISION 0x02
|
||||
#define WM8350_SYSTEM_CONTROL_1 0x03
|
||||
#define WM8350_SYSTEM_CONTROL_2 0x04
|
||||
#define WM8350_SYSTEM_HIBERNATE 0x05
|
||||
#define WM8350_INTERFACE_CONTROL 0x06
|
||||
#define WM8350_POWER_MGMT_1 0x08
|
||||
#define WM8350_POWER_MGMT_2 0x09
|
||||
#define WM8350_POWER_MGMT_3 0x0A
|
||||
#define WM8350_POWER_MGMT_4 0x0B
|
||||
#define WM8350_POWER_MGMT_5 0x0C
|
||||
#define WM8350_POWER_MGMT_6 0x0D
|
||||
#define WM8350_POWER_MGMT_7 0x0E
|
||||
|
||||
#define WM8350_SYSTEM_INTERRUPTS 0x18
|
||||
#define WM8350_INT_STATUS_1 0x19
|
||||
#define WM8350_INT_STATUS_2 0x1A
|
||||
#define WM8350_POWER_UP_INT_STATUS 0x1B
|
||||
#define WM8350_UNDER_VOLTAGE_INT_STATUS 0x1C
|
||||
#define WM8350_OVER_CURRENT_INT_STATUS 0x1D
|
||||
#define WM8350_GPIO_INT_STATUS 0x1E
|
||||
#define WM8350_COMPARATOR_INT_STATUS 0x1F
|
||||
#define WM8350_SYSTEM_INTERRUPTS_MASK 0x20
|
||||
#define WM8350_INT_STATUS_1_MASK 0x21
|
||||
#define WM8350_INT_STATUS_2_MASK 0x22
|
||||
#define WM8350_POWER_UP_INT_STATUS_MASK 0x23
|
||||
#define WM8350_UNDER_VOLTAGE_INT_STATUS_MASK 0x24
|
||||
#define WM8350_OVER_CURRENT_INT_STATUS_MASK 0x25
|
||||
#define WM8350_GPIO_INT_STATUS_MASK 0x26
|
||||
#define WM8350_COMPARATOR_INT_STATUS_MASK 0x27
|
||||
#define WM8350_CHARGER_OVERRIDES 0xE2
|
||||
#define WM8350_MISC_OVERRIDES 0xE3
|
||||
#define WM8350_COMPARATOR_OVERRIDES 0xE7
|
||||
#define WM8350_STATE_MACHINE_STATUS 0xE9
|
||||
|
||||
#define WM8350_MAX_REGISTER 0xFF
|
||||
|
||||
#define WM8350_UNLOCK_KEY 0x0013
|
||||
#define WM8350_LOCK_KEY 0x0000
|
||||
|
||||
/*
|
||||
* Field Definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* R0 (0x00) - Reset/ID
|
||||
*/
|
||||
#define WM8350_SW_RESET_CHIP_ID_MASK 0xFFFF
|
||||
|
||||
/*
|
||||
* R1 (0x01) - ID
|
||||
*/
|
||||
#define WM8350_CHIP_REV_MASK 0x7000
|
||||
#define WM8350_CONF_STS_MASK 0x0C00
|
||||
#define WM8350_CUST_ID_MASK 0x00FF
|
||||
|
||||
/*
|
||||
* R2 (0x02) - Revision
|
||||
*/
|
||||
#define WM8350_MASK_REV_MASK 0x00FF
|
||||
|
||||
/*
|
||||
* R3 (0x03) - System Control 1
|
||||
*/
|
||||
#define WM8350_CHIP_ON 0x8000
|
||||
#define WM8350_POWERCYCLE 0x2000
|
||||
#define WM8350_VCC_FAULT_OV 0x1000
|
||||
#define WM8350_REG_RSTB_TIME_MASK 0x0C00
|
||||
#define WM8350_BG_SLEEP 0x0200
|
||||
#define WM8350_MEM_VALID 0x0020
|
||||
#define WM8350_CHIP_SET_UP 0x0010
|
||||
#define WM8350_ON_DEB_T 0x0008
|
||||
#define WM8350_ON_POL 0x0002
|
||||
#define WM8350_IRQ_POL 0x0001
|
||||
|
||||
/*
|
||||
* R4 (0x04) - System Control 2
|
||||
*/
|
||||
#define WM8350_USB_SUSPEND_8MA 0x8000
|
||||
#define WM8350_USB_SUSPEND 0x4000
|
||||
#define WM8350_USB_MSTR 0x2000
|
||||
#define WM8350_USB_MSTR_SRC 0x1000
|
||||
#define WM8350_USB_500MA 0x0800
|
||||
#define WM8350_USB_NOLIM 0x0400
|
||||
|
||||
/*
|
||||
* R5 (0x05) - System Hibernate
|
||||
*/
|
||||
#define WM8350_HIBERNATE 0x8000
|
||||
#define WM8350_WDOG_HIB_MODE 0x0080
|
||||
#define WM8350_REG_HIB_STARTUP_SEQ 0x0040
|
||||
#define WM8350_REG_RESET_HIB_MODE 0x0020
|
||||
#define WM8350_RST_HIB_MODE 0x0010
|
||||
#define WM8350_IRQ_HIB_MODE 0x0008
|
||||
#define WM8350_MEMRST_HIB_MODE 0x0004
|
||||
#define WM8350_PCCOMP_HIB_MODE 0x0002
|
||||
#define WM8350_TEMPMON_HIB_MODE 0x0001
|
||||
|
||||
/*
|
||||
* R6 (0x06) - Interface Control
|
||||
*/
|
||||
#define WM8350_USE_DEV_PINS 0x8000
|
||||
#define WM8350_USE_DEV_PINS_MASK 0x8000
|
||||
#define WM8350_USE_DEV_PINS_SHIFT 15
|
||||
#define WM8350_DEV_ADDR_MASK 0x6000
|
||||
#define WM8350_DEV_ADDR_SHIFT 13
|
||||
#define WM8350_CONFIG_DONE 0x1000
|
||||
#define WM8350_CONFIG_DONE_MASK 0x1000
|
||||
#define WM8350_CONFIG_DONE_SHIFT 12
|
||||
#define WM8350_RECONFIG_AT_ON 0x0800
|
||||
#define WM8350_RECONFIG_AT_ON_MASK 0x0800
|
||||
#define WM8350_RECONFIG_AT_ON_SHIFT 11
|
||||
#define WM8350_AUTOINC 0x0200
|
||||
#define WM8350_AUTOINC_MASK 0x0200
|
||||
#define WM8350_AUTOINC_SHIFT 9
|
||||
#define WM8350_ARA 0x0100
|
||||
#define WM8350_ARA_MASK 0x0100
|
||||
#define WM8350_ARA_SHIFT 8
|
||||
#define WM8350_SPI_CFG 0x0008
|
||||
#define WM8350_SPI_CFG_MASK 0x0008
|
||||
#define WM8350_SPI_CFG_SHIFT 3
|
||||
#define WM8350_SPI_4WIRE 0x0004
|
||||
#define WM8350_SPI_4WIRE_MASK 0x0004
|
||||
#define WM8350_SPI_4WIRE_SHIFT 2
|
||||
#define WM8350_SPI_3WIRE 0x0002
|
||||
#define WM8350_SPI_3WIRE_MASK 0x0002
|
||||
#define WM8350_SPI_3WIRE_SHIFT 1
|
||||
|
||||
/* Bit values for R06 (0x06) */
|
||||
#define WM8350_USE_DEV_PINS_PRIMARY 0
|
||||
#define WM8350_USE_DEV_PINS_DEV 1
|
||||
|
||||
#define WM8350_DEV_ADDR_34 0
|
||||
#define WM8350_DEV_ADDR_36 1
|
||||
#define WM8350_DEV_ADDR_3C 2
|
||||
#define WM8350_DEV_ADDR_3E 3
|
||||
|
||||
#define WM8350_CONFIG_DONE_OFF 0
|
||||
#define WM8350_CONFIG_DONE_DONE 1
|
||||
|
||||
#define WM8350_RECONFIG_AT_ON_OFF 0
|
||||
#define WM8350_RECONFIG_AT_ON_ON 1
|
||||
|
||||
#define WM8350_AUTOINC_OFF 0
|
||||
#define WM8350_AUTOINC_ON 1
|
||||
|
||||
#define WM8350_ARA_OFF 0
|
||||
#define WM8350_ARA_ON 1
|
||||
|
||||
#define WM8350_SPI_CFG_CMOS 0
|
||||
#define WM8350_SPI_CFG_OD 1
|
||||
|
||||
#define WM8350_SPI_4WIRE_3WIRE 0
|
||||
#define WM8350_SPI_4WIRE_4WIRE 1
|
||||
|
||||
#define WM8350_SPI_3WIRE_I2C 0
|
||||
#define WM8350_SPI_3WIRE_SPI 1
|
||||
|
||||
/*
|
||||
* R8 (0x08) - Power mgmt (1)
|
||||
*/
|
||||
#define WM8350_CODEC_ISEL_MASK 0xC000
|
||||
#define WM8350_VBUFEN 0x2000
|
||||
#define WM8350_OUTPUT_DRAIN_EN 0x0400
|
||||
#define WM8350_MIC_DET_ENA 0x0100
|
||||
#define WM8350_BIASEN 0x0020
|
||||
#define WM8350_MICBEN 0x0010
|
||||
#define WM8350_VMIDEN 0x0004
|
||||
#define WM8350_VMID_MASK 0x0003
|
||||
#define WM8350_VMID_SHIFT 0
|
||||
|
||||
/*
|
||||
* R9 (0x09) - Power mgmt (2)
|
||||
*/
|
||||
#define WM8350_IN3R_ENA 0x0800
|
||||
#define WM8350_IN3L_ENA 0x0400
|
||||
#define WM8350_INR_ENA 0x0200
|
||||
#define WM8350_INL_ENA 0x0100
|
||||
#define WM8350_MIXINR_ENA 0x0080
|
||||
#define WM8350_MIXINL_ENA 0x0040
|
||||
#define WM8350_OUT4_ENA 0x0020
|
||||
#define WM8350_OUT3_ENA 0x0010
|
||||
#define WM8350_MIXOUTR_ENA 0x0002
|
||||
#define WM8350_MIXOUTL_ENA 0x0001
|
||||
|
||||
/*
|
||||
* R10 (0x0A) - Power mgmt (3)
|
||||
*/
|
||||
#define WM8350_IN3R_TO_OUT2R 0x0080
|
||||
#define WM8350_OUT2R_ENA 0x0008
|
||||
#define WM8350_OUT2L_ENA 0x0004
|
||||
#define WM8350_OUT1R_ENA 0x0002
|
||||
#define WM8350_OUT1L_ENA 0x0001
|
||||
|
||||
/*
|
||||
* R11 (0x0B) - Power mgmt (4)
|
||||
*/
|
||||
#define WM8350_SYSCLK_ENA 0x4000
|
||||
#define WM8350_ADC_HPF_ENA 0x2000
|
||||
#define WM8350_FLL_ENA 0x0800
|
||||
#define WM8350_FLL_OSC_ENA 0x0400
|
||||
#define WM8350_TOCLK_ENA 0x0100
|
||||
#define WM8350_DACR_ENA 0x0020
|
||||
#define WM8350_DACL_ENA 0x0010
|
||||
#define WM8350_ADCR_ENA 0x0008
|
||||
#define WM8350_ADCL_ENA 0x0004
|
||||
|
||||
/*
|
||||
* R12 (0x0C) - Power mgmt (5)
|
||||
*/
|
||||
#define WM8350_CODEC_ENA 0x1000
|
||||
#define WM8350_RTC_TICK_ENA 0x0800
|
||||
#define WM8350_OSC32K_ENA 0x0400
|
||||
#define WM8350_CHG_ENA 0x0200
|
||||
#define WM8350_ACC_DET_ENA 0x0100
|
||||
#define WM8350_AUXADC_ENA 0x0080
|
||||
#define WM8350_DCMP4_ENA 0x0008
|
||||
#define WM8350_DCMP3_ENA 0x0004
|
||||
#define WM8350_DCMP2_ENA 0x0002
|
||||
#define WM8350_DCMP1_ENA 0x0001
|
||||
|
||||
/*
|
||||
* R13 (0x0D) - Power mgmt (6)
|
||||
*/
|
||||
#define WM8350_LS_ENA 0x8000
|
||||
#define WM8350_LDO4_ENA 0x0800
|
||||
#define WM8350_LDO3_ENA 0x0400
|
||||
#define WM8350_LDO2_ENA 0x0200
|
||||
#define WM8350_LDO1_ENA 0x0100
|
||||
#define WM8350_DC6_ENA 0x0020
|
||||
#define WM8350_DC5_ENA 0x0010
|
||||
#define WM8350_DC4_ENA 0x0008
|
||||
#define WM8350_DC3_ENA 0x0004
|
||||
#define WM8350_DC2_ENA 0x0002
|
||||
#define WM8350_DC1_ENA 0x0001
|
||||
|
||||
/*
|
||||
* R14 (0x0E) - Power mgmt (7)
|
||||
*/
|
||||
#define WM8350_CS2_ENA 0x0002
|
||||
#define WM8350_CS1_ENA 0x0001
|
||||
|
||||
/*
|
||||
* R24 (0x18) - System Interrupts
|
||||
*/
|
||||
#define WM8350_OC_INT 0x2000
|
||||
#define WM8350_UV_INT 0x1000
|
||||
#define WM8350_PUTO_INT 0x0800
|
||||
#define WM8350_CS_INT 0x0200
|
||||
#define WM8350_EXT_INT 0x0100
|
||||
#define WM8350_CODEC_INT 0x0080
|
||||
#define WM8350_GP_INT 0x0040
|
||||
#define WM8350_AUXADC_INT 0x0020
|
||||
#define WM8350_RTC_INT 0x0010
|
||||
#define WM8350_SYS_INT 0x0008
|
||||
#define WM8350_CHG_INT 0x0004
|
||||
#define WM8350_USB_INT 0x0002
|
||||
#define WM8350_WKUP_INT 0x0001
|
||||
|
||||
/*
|
||||
* R25 (0x19) - Interrupt Status 1
|
||||
*/
|
||||
#define WM8350_CHG_BAT_HOT_EINT 0x8000
|
||||
#define WM8350_CHG_BAT_COLD_EINT 0x4000
|
||||
#define WM8350_CHG_BAT_FAIL_EINT 0x2000
|
||||
#define WM8350_CHG_TO_EINT 0x1000
|
||||
#define WM8350_CHG_END_EINT 0x0800
|
||||
#define WM8350_CHG_START_EINT 0x0400
|
||||
#define WM8350_CHG_FAST_RDY_EINT 0x0200
|
||||
#define WM8350_RTC_PER_EINT 0x0080
|
||||
#define WM8350_RTC_SEC_EINT 0x0040
|
||||
#define WM8350_RTC_ALM_EINT 0x0020
|
||||
#define WM8350_CHG_VBATT_LT_3P9_EINT 0x0004
|
||||
#define WM8350_CHG_VBATT_LT_3P1_EINT 0x0002
|
||||
#define WM8350_CHG_VBATT_LT_2P85_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R26 (0x1A) - Interrupt Status 2
|
||||
*/
|
||||
#define WM8350_CS1_EINT 0x2000
|
||||
#define WM8350_CS2_EINT 0x1000
|
||||
#define WM8350_USB_LIMIT_EINT 0x0400
|
||||
#define WM8350_AUXADC_DATARDY_EINT 0x0100
|
||||
#define WM8350_AUXADC_DCOMP4_EINT 0x0080
|
||||
#define WM8350_AUXADC_DCOMP3_EINT 0x0040
|
||||
#define WM8350_AUXADC_DCOMP2_EINT 0x0020
|
||||
#define WM8350_AUXADC_DCOMP1_EINT 0x0010
|
||||
#define WM8350_SYS_HYST_COMP_FAIL_EINT 0x0008
|
||||
#define WM8350_SYS_CHIP_GT115_EINT 0x0004
|
||||
#define WM8350_SYS_CHIP_GT140_EINT 0x0002
|
||||
#define WM8350_SYS_WDOG_TO_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R27 (0x1B) - Power Up Interrupt Status
|
||||
*/
|
||||
#define WM8350_PUTO_LDO4_EINT 0x0800
|
||||
#define WM8350_PUTO_LDO3_EINT 0x0400
|
||||
#define WM8350_PUTO_LDO2_EINT 0x0200
|
||||
#define WM8350_PUTO_LDO1_EINT 0x0100
|
||||
#define WM8350_PUTO_DC6_EINT 0x0020
|
||||
#define WM8350_PUTO_DC5_EINT 0x0010
|
||||
#define WM8350_PUTO_DC4_EINT 0x0008
|
||||
#define WM8350_PUTO_DC3_EINT 0x0004
|
||||
#define WM8350_PUTO_DC2_EINT 0x0002
|
||||
#define WM8350_PUTO_DC1_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R28 (0x1C) - Under Voltage Interrupt status
|
||||
*/
|
||||
#define WM8350_UV_LDO4_EINT 0x0800
|
||||
#define WM8350_UV_LDO3_EINT 0x0400
|
||||
#define WM8350_UV_LDO2_EINT 0x0200
|
||||
#define WM8350_UV_LDO1_EINT 0x0100
|
||||
#define WM8350_UV_DC6_EINT 0x0020
|
||||
#define WM8350_UV_DC5_EINT 0x0010
|
||||
#define WM8350_UV_DC4_EINT 0x0008
|
||||
#define WM8350_UV_DC3_EINT 0x0004
|
||||
#define WM8350_UV_DC2_EINT 0x0002
|
||||
#define WM8350_UV_DC1_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R29 (0x1D) - Over Current Interrupt status
|
||||
*/
|
||||
#define WM8350_OC_LS_EINT 0x8000
|
||||
|
||||
/*
|
||||
* R30 (0x1E) - GPIO Interrupt Status
|
||||
*/
|
||||
#define WM8350_GP12_EINT 0x1000
|
||||
#define WM8350_GP11_EINT 0x0800
|
||||
#define WM8350_GP10_EINT 0x0400
|
||||
#define WM8350_GP9_EINT 0x0200
|
||||
#define WM8350_GP8_EINT 0x0100
|
||||
#define WM8350_GP7_EINT 0x0080
|
||||
#define WM8350_GP6_EINT 0x0040
|
||||
#define WM8350_GP5_EINT 0x0020
|
||||
#define WM8350_GP4_EINT 0x0010
|
||||
#define WM8350_GP3_EINT 0x0008
|
||||
#define WM8350_GP2_EINT 0x0004
|
||||
#define WM8350_GP1_EINT 0x0002
|
||||
#define WM8350_GP0_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R31 (0x1F) - Comparator Interrupt Status
|
||||
*/
|
||||
#define WM8350_EXT_USB_FB_EINT 0x8000
|
||||
#define WM8350_EXT_WALL_FB_EINT 0x4000
|
||||
#define WM8350_EXT_BAT_FB_EINT 0x2000
|
||||
#define WM8350_CODEC_JCK_DET_L_EINT 0x0800
|
||||
#define WM8350_CODEC_JCK_DET_R_EINT 0x0400
|
||||
#define WM8350_CODEC_MICSCD_EINT 0x0200
|
||||
#define WM8350_CODEC_MICD_EINT 0x0100
|
||||
#define WM8350_WKUP_OFF_STATE_EINT 0x0040
|
||||
#define WM8350_WKUP_HIB_STATE_EINT 0x0020
|
||||
#define WM8350_WKUP_CONV_FAULT_EINT 0x0010
|
||||
#define WM8350_WKUP_WDOG_RST_EINT 0x0008
|
||||
#define WM8350_WKUP_GP_PWR_ON_EINT 0x0004
|
||||
#define WM8350_WKUP_ONKEY_EINT 0x0002
|
||||
#define WM8350_WKUP_GP_WAKEUP_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R32 (0x20) - System Interrupts Mask
|
||||
*/
|
||||
#define WM8350_IM_OC_INT 0x2000
|
||||
#define WM8350_IM_UV_INT 0x1000
|
||||
#define WM8350_IM_PUTO_INT 0x0800
|
||||
#define WM8350_IM_SPARE_INT 0x0400
|
||||
#define WM8350_IM_CS_INT 0x0200
|
||||
#define WM8350_IM_EXT_INT 0x0100
|
||||
#define WM8350_IM_CODEC_INT 0x0080
|
||||
#define WM8350_IM_GP_INT 0x0040
|
||||
#define WM8350_IM_AUXADC_INT 0x0020
|
||||
#define WM8350_IM_RTC_INT 0x0010
|
||||
#define WM8350_IM_SYS_INT 0x0008
|
||||
#define WM8350_IM_CHG_INT 0x0004
|
||||
#define WM8350_IM_USB_INT 0x0002
|
||||
#define WM8350_IM_WKUP_INT 0x0001
|
||||
|
||||
/*
|
||||
* R33 (0x21) - Interrupt Status 1 Mask
|
||||
*/
|
||||
#define WM8350_IM_CHG_BAT_HOT_EINT 0x8000
|
||||
#define WM8350_IM_CHG_BAT_COLD_EINT 0x4000
|
||||
#define WM8350_IM_CHG_BAT_FAIL_EINT 0x2000
|
||||
#define WM8350_IM_CHG_TO_EINT 0x1000
|
||||
#define WM8350_IM_CHG_END_EINT 0x0800
|
||||
#define WM8350_IM_CHG_START_EINT 0x0400
|
||||
#define WM8350_IM_CHG_FAST_RDY_EINT 0x0200
|
||||
#define WM8350_IM_RTC_PER_EINT 0x0080
|
||||
#define WM8350_IM_RTC_SEC_EINT 0x0040
|
||||
#define WM8350_IM_RTC_ALM_EINT 0x0020
|
||||
#define WM8350_IM_CHG_VBATT_LT_3P9_EINT 0x0004
|
||||
#define WM8350_IM_CHG_VBATT_LT_3P1_EINT 0x0002
|
||||
#define WM8350_IM_CHG_VBATT_LT_2P85_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R34 (0x22) - Interrupt Status 2 Mask
|
||||
*/
|
||||
#define WM8350_IM_SPARE2_EINT 0x8000
|
||||
#define WM8350_IM_SPARE1_EINT 0x4000
|
||||
#define WM8350_IM_CS1_EINT 0x2000
|
||||
#define WM8350_IM_CS2_EINT 0x1000
|
||||
#define WM8350_IM_USB_LIMIT_EINT 0x0400
|
||||
#define WM8350_IM_AUXADC_DATARDY_EINT 0x0100
|
||||
#define WM8350_IM_AUXADC_DCOMP4_EINT 0x0080
|
||||
#define WM8350_IM_AUXADC_DCOMP3_EINT 0x0040
|
||||
#define WM8350_IM_AUXADC_DCOMP2_EINT 0x0020
|
||||
#define WM8350_IM_AUXADC_DCOMP1_EINT 0x0010
|
||||
#define WM8350_IM_SYS_HYST_COMP_FAIL_EINT 0x0008
|
||||
#define WM8350_IM_SYS_CHIP_GT115_EINT 0x0004
|
||||
#define WM8350_IM_SYS_CHIP_GT140_EINT 0x0002
|
||||
#define WM8350_IM_SYS_WDOG_TO_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R35 (0x23) - Power Up Interrupt Status Mask
|
||||
*/
|
||||
#define WM8350_IM_PUTO_LDO4_EINT 0x0800
|
||||
#define WM8350_IM_PUTO_LDO3_EINT 0x0400
|
||||
#define WM8350_IM_PUTO_LDO2_EINT 0x0200
|
||||
#define WM8350_IM_PUTO_LDO1_EINT 0x0100
|
||||
#define WM8350_IM_PUTO_DC6_EINT 0x0020
|
||||
#define WM8350_IM_PUTO_DC5_EINT 0x0010
|
||||
#define WM8350_IM_PUTO_DC4_EINT 0x0008
|
||||
#define WM8350_IM_PUTO_DC3_EINT 0x0004
|
||||
#define WM8350_IM_PUTO_DC2_EINT 0x0002
|
||||
#define WM8350_IM_PUTO_DC1_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R36 (0x24) - Under Voltage Interrupt status Mask
|
||||
*/
|
||||
#define WM8350_IM_UV_LDO4_EINT 0x0800
|
||||
#define WM8350_IM_UV_LDO3_EINT 0x0400
|
||||
#define WM8350_IM_UV_LDO2_EINT 0x0200
|
||||
#define WM8350_IM_UV_LDO1_EINT 0x0100
|
||||
#define WM8350_IM_UV_DC6_EINT 0x0020
|
||||
#define WM8350_IM_UV_DC5_EINT 0x0010
|
||||
#define WM8350_IM_UV_DC4_EINT 0x0008
|
||||
#define WM8350_IM_UV_DC3_EINT 0x0004
|
||||
#define WM8350_IM_UV_DC2_EINT 0x0002
|
||||
#define WM8350_IM_UV_DC1_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R37 (0x25) - Over Current Interrupt status Mask
|
||||
*/
|
||||
#define WM8350_IM_OC_LS_EINT 0x8000
|
||||
|
||||
/*
|
||||
* R38 (0x26) - GPIO Interrupt Status Mask
|
||||
*/
|
||||
#define WM8350_IM_GP12_EINT 0x1000
|
||||
#define WM8350_IM_GP11_EINT 0x0800
|
||||
#define WM8350_IM_GP10_EINT 0x0400
|
||||
#define WM8350_IM_GP9_EINT 0x0200
|
||||
#define WM8350_IM_GP8_EINT 0x0100
|
||||
#define WM8350_IM_GP7_EINT 0x0080
|
||||
#define WM8350_IM_GP6_EINT 0x0040
|
||||
#define WM8350_IM_GP5_EINT 0x0020
|
||||
#define WM8350_IM_GP4_EINT 0x0010
|
||||
#define WM8350_IM_GP3_EINT 0x0008
|
||||
#define WM8350_IM_GP2_EINT 0x0004
|
||||
#define WM8350_IM_GP1_EINT 0x0002
|
||||
#define WM8350_IM_GP0_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R39 (0x27) - Comparator Interrupt Status Mask
|
||||
*/
|
||||
#define WM8350_IM_EXT_USB_FB_EINT 0x8000
|
||||
#define WM8350_IM_EXT_WALL_FB_EINT 0x4000
|
||||
#define WM8350_IM_EXT_BAT_FB_EINT 0x2000
|
||||
#define WM8350_IM_CODEC_JCK_DET_L_EINT 0x0800
|
||||
#define WM8350_IM_CODEC_JCK_DET_R_EINT 0x0400
|
||||
#define WM8350_IM_CODEC_MICSCD_EINT 0x0200
|
||||
#define WM8350_IM_CODEC_MICD_EINT 0x0100
|
||||
#define WM8350_IM_WKUP_OFF_STATE_EINT 0x0040
|
||||
#define WM8350_IM_WKUP_HIB_STATE_EINT 0x0020
|
||||
#define WM8350_IM_WKUP_CONV_FAULT_EINT 0x0010
|
||||
#define WM8350_IM_WKUP_WDOG_RST_EINT 0x0008
|
||||
#define WM8350_IM_WKUP_GP_PWR_ON_EINT 0x0004
|
||||
#define WM8350_IM_WKUP_ONKEY_EINT 0x0002
|
||||
#define WM8350_IM_WKUP_GP_WAKEUP_EINT 0x0001
|
||||
|
||||
/*
|
||||
* R220 (0xDC) - RAM BIST 1
|
||||
*/
|
||||
#define WM8350_READ_STATUS 0x0800
|
||||
#define WM8350_TSTRAM_CLK 0x0100
|
||||
#define WM8350_TSTRAM_CLK_ENA 0x0080
|
||||
#define WM8350_STARTSEQ 0x0040
|
||||
#define WM8350_READ_SRC 0x0020
|
||||
#define WM8350_COUNT_DIR 0x0010
|
||||
#define WM8350_TSTRAM_MODE_MASK 0x000E
|
||||
#define WM8350_TSTRAM_ENA 0x0001
|
||||
|
||||
/*
|
||||
* R225 (0xE1) - DCDC/LDO status
|
||||
*/
|
||||
#define WM8350_LS_STS 0x8000
|
||||
#define WM8350_LDO4_STS 0x0800
|
||||
#define WM8350_LDO3_STS 0x0400
|
||||
#define WM8350_LDO2_STS 0x0200
|
||||
#define WM8350_LDO1_STS 0x0100
|
||||
#define WM8350_DC6_STS 0x0020
|
||||
#define WM8350_DC5_STS 0x0010
|
||||
#define WM8350_DC4_STS 0x0008
|
||||
#define WM8350_DC3_STS 0x0004
|
||||
#define WM8350_DC2_STS 0x0002
|
||||
#define WM8350_DC1_STS 0x0001
|
||||
|
||||
/*
|
||||
* R226 (0xE2) - Charger status
|
||||
*/
|
||||
#define WM8350_CHG_BATT_HOT_OVRDE 0x8000
|
||||
#define WM8350_CHG_BATT_COLD_OVRDE 0x4000
|
||||
|
||||
/*
|
||||
* R227 (0xE3) - Misc Overrides
|
||||
*/
|
||||
#define WM8350_USB_LIMIT_OVRDE 0x0400
|
||||
|
||||
/*
|
||||
* R227 (0xE7) - Comparator Overrides
|
||||
*/
|
||||
#define WM8350_USB_FB_OVRDE 0x8000
|
||||
#define WM8350_WALL_FB_OVRDE 0x4000
|
||||
#define WM8350_BATT_FB_OVRDE 0x2000
|
||||
|
||||
|
||||
/*
|
||||
* R233 (0xE9) - State Machinine Status
|
||||
*/
|
||||
#define WM8350_USB_SM_MASK 0x0700
|
||||
#define WM8350_USB_SM_SHIFT 8
|
||||
|
||||
#define WM8350_USB_SM_100_SLV 1
|
||||
#define WM8350_USB_SM_500_SLV 5
|
||||
#define WM8350_USB_SM_STDBY_SLV 7
|
||||
|
||||
/* WM8350 wake up conditions */
|
||||
#define WM8350_IRQ_WKUP_OFF_STATE 43
|
||||
#define WM8350_IRQ_WKUP_HIB_STATE 44
|
||||
#define WM8350_IRQ_WKUP_CONV_FAULT 45
|
||||
#define WM8350_IRQ_WKUP_WDOG_RST 46
|
||||
#define WM8350_IRQ_WKUP_GP_PWR_ON 47
|
||||
#define WM8350_IRQ_WKUP_ONKEY 48
|
||||
#define WM8350_IRQ_WKUP_GP_WAKEUP 49
|
||||
|
||||
/* wm8350 chip revisions */
|
||||
#define WM8350_REV_E 0x4
|
||||
#define WM8350_REV_F 0x5
|
||||
#define WM8350_REV_G 0x6
|
||||
#define WM8350_REV_H 0x7
|
||||
|
||||
#define WM8350_NUM_IRQ 63
|
||||
|
||||
#define WM8350_NUM_IRQ_REGS 7
|
||||
|
||||
extern const struct regmap_config wm8350_regmap;
|
||||
|
||||
struct wm8350;
|
||||
|
||||
struct wm8350_hwmon {
|
||||
struct platform_device *pdev;
|
||||
struct device *classdev;
|
||||
};
|
||||
|
||||
struct wm8350 {
|
||||
struct device *dev;
|
||||
|
||||
/* device IO */
|
||||
struct regmap *regmap;
|
||||
bool unlocked;
|
||||
|
||||
struct mutex auxadc_mutex;
|
||||
struct completion auxadc_done;
|
||||
|
||||
/* Interrupt handling */
|
||||
struct mutex irq_lock;
|
||||
int chip_irq;
|
||||
int irq_base;
|
||||
u16 irq_masks[WM8350_NUM_IRQ_REGS];
|
||||
|
||||
/* Client devices */
|
||||
struct wm8350_codec codec;
|
||||
struct wm8350_gpio gpio;
|
||||
struct wm8350_hwmon hwmon;
|
||||
struct wm8350_pmic pmic;
|
||||
struct wm8350_power power;
|
||||
struct wm8350_rtc rtc;
|
||||
struct wm8350_wdt wdt;
|
||||
};
|
||||
|
||||
/**
|
||||
* Data to be supplied by the platform to initialise the WM8350.
|
||||
*
|
||||
* @init: Function called during driver initialisation. Should be
|
||||
* used by the platform to configure GPIO functions and similar.
|
||||
* @irq_high: Set if WM8350 IRQ is active high.
|
||||
* @irq_base: Base IRQ for genirq (not currently used).
|
||||
* @gpio_base: Base for gpiolib.
|
||||
*/
|
||||
struct wm8350_platform_data {
|
||||
int (*init)(struct wm8350 *wm8350);
|
||||
int irq_high;
|
||||
int irq_base;
|
||||
int gpio_base;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* WM8350 device initialisation and exit.
|
||||
*/
|
||||
int wm8350_device_init(struct wm8350 *wm8350, int irq,
|
||||
struct wm8350_platform_data *pdata);
|
||||
|
||||
/*
|
||||
* WM8350 device IO
|
||||
*/
|
||||
int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
|
||||
int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
|
||||
u16 wm8350_reg_read(struct wm8350 *wm8350, int reg);
|
||||
int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val);
|
||||
int wm8350_reg_lock(struct wm8350 *wm8350);
|
||||
int wm8350_reg_unlock(struct wm8350 *wm8350);
|
||||
int wm8350_block_read(struct wm8350 *wm8350, int reg, int size, u16 *dest);
|
||||
int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
|
||||
|
||||
/*
|
||||
* WM8350 internal interrupts
|
||||
*/
|
||||
static inline int wm8350_register_irq(struct wm8350 *wm8350, int irq,
|
||||
irq_handler_t handler,
|
||||
unsigned long flags,
|
||||
const char *name, void *data)
|
||||
{
|
||||
if (!wm8350->irq_base)
|
||||
return -ENODEV;
|
||||
|
||||
return request_threaded_irq(irq + wm8350->irq_base, NULL,
|
||||
handler, flags | IRQF_ONESHOT, name, data);
|
||||
}
|
||||
|
||||
static inline void wm8350_free_irq(struct wm8350 *wm8350, int irq, void *data)
|
||||
{
|
||||
free_irq(irq + wm8350->irq_base, data);
|
||||
}
|
||||
|
||||
static inline void wm8350_mask_irq(struct wm8350 *wm8350, int irq)
|
||||
{
|
||||
disable_irq(irq + wm8350->irq_base);
|
||||
}
|
||||
|
||||
static inline void wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
|
||||
{
|
||||
enable_irq(irq + wm8350->irq_base);
|
||||
}
|
||||
|
||||
int wm8350_irq_init(struct wm8350 *wm8350, int irq,
|
||||
struct wm8350_platform_data *pdata);
|
||||
int wm8350_irq_exit(struct wm8350 *wm8350);
|
||||
|
||||
#endif
|
||||
@@ -1,140 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* include/linux/mfd/wm8994/core.h -- Core interface for WM8994
|
||||
*
|
||||
* Copyright 2009 Wolfson Microelectronics PLC.
|
||||
*
|
||||
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
*/
|
||||
|
||||
#ifndef __MFD_WM8994_CORE_H__
|
||||
#define __MFD_WM8994_CORE_H__
|
||||
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <linux/mfd/wm8994/pdata.h>
|
||||
|
||||
enum wm8994_type {
|
||||
WM8994 = 0,
|
||||
WM8958 = 1,
|
||||
WM1811 = 2,
|
||||
};
|
||||
|
||||
struct regulator_dev;
|
||||
struct regulator_bulk_data;
|
||||
struct irq_domain;
|
||||
|
||||
#define WM8994_NUM_GPIO_REGS 11
|
||||
#define WM8994_NUM_LDO_REGS 2
|
||||
#define WM8994_NUM_IRQ_REGS 2
|
||||
|
||||
#define WM8994_IRQ_TEMP_SHUT 0
|
||||
#define WM8994_IRQ_MIC1_DET 1
|
||||
#define WM8994_IRQ_MIC1_SHRT 2
|
||||
#define WM8994_IRQ_MIC2_DET 3
|
||||
#define WM8994_IRQ_MIC2_SHRT 4
|
||||
#define WM8994_IRQ_FLL1_LOCK 5
|
||||
#define WM8994_IRQ_FLL2_LOCK 6
|
||||
#define WM8994_IRQ_SRC1_LOCK 7
|
||||
#define WM8994_IRQ_SRC2_LOCK 8
|
||||
#define WM8994_IRQ_AIF1DRC1_SIG_DET 9
|
||||
#define WM8994_IRQ_AIF1DRC2_SIG_DET 10
|
||||
#define WM8994_IRQ_AIF2DRC_SIG_DET 11
|
||||
#define WM8994_IRQ_FIFOS_ERR 12
|
||||
#define WM8994_IRQ_WSEQ_DONE 13
|
||||
#define WM8994_IRQ_DCS_DONE 14
|
||||
#define WM8994_IRQ_TEMP_WARN 15
|
||||
|
||||
/* GPIOs in the chip are numbered from 1-11 */
|
||||
#define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN)
|
||||
|
||||
struct wm8994 {
|
||||
struct wm8994_pdata pdata;
|
||||
|
||||
enum wm8994_type type;
|
||||
int revision;
|
||||
int cust_id;
|
||||
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
|
||||
bool ldo_ena_always_driven;
|
||||
|
||||
int gpio_base;
|
||||
int irq_base;
|
||||
|
||||
int irq;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
struct irq_domain *edge_irq;
|
||||
|
||||
/* Used over suspend/resume */
|
||||
bool suspended;
|
||||
|
||||
struct regulator_dev *dbvdd;
|
||||
int num_supplies;
|
||||
struct regulator_bulk_data *supplies;
|
||||
};
|
||||
|
||||
/* Device I/O API */
|
||||
|
||||
static inline int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg)
|
||||
{
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(wm8994->regmap, reg, &val);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
else
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg,
|
||||
unsigned short val)
|
||||
{
|
||||
return regmap_write(wm8994->regmap, reg, val);
|
||||
}
|
||||
|
||||
static inline int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
|
||||
int count, u16 *buf)
|
||||
{
|
||||
return regmap_bulk_read(wm8994->regmap, reg, buf, count);
|
||||
}
|
||||
|
||||
static inline int wm8994_bulk_write(struct wm8994 *wm8994, unsigned short reg,
|
||||
int count, const u16 *buf)
|
||||
{
|
||||
return regmap_raw_write(wm8994->regmap, reg, buf, count * sizeof(u16));
|
||||
}
|
||||
|
||||
static inline int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
|
||||
unsigned short mask, unsigned short val)
|
||||
{
|
||||
return regmap_update_bits(wm8994->regmap, reg, mask, val);
|
||||
}
|
||||
|
||||
/* Helper to save on boilerplate */
|
||||
static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq,
|
||||
irq_handler_t handler, const char *name,
|
||||
void *data)
|
||||
{
|
||||
if (!wm8994->irq_data)
|
||||
return -EINVAL;
|
||||
return request_threaded_irq(regmap_irq_get_virq(wm8994->irq_data, irq),
|
||||
NULL, handler, IRQF_TRIGGER_RISING, name,
|
||||
data);
|
||||
}
|
||||
static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data)
|
||||
{
|
||||
if (!wm8994->irq_data)
|
||||
return;
|
||||
free_irq(regmap_irq_get_virq(wm8994->irq_data, irq), data);
|
||||
}
|
||||
|
||||
int wm8994_irq_init(struct wm8994 *wm8994);
|
||||
void wm8994_irq_exit(struct wm8994 *wm8994);
|
||||
|
||||
#endif
|
||||
@@ -1,188 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* linux/include/linux/mmc/core.h
|
||||
*/
|
||||
#ifndef LINUX_MMC_CORE_H
|
||||
#define LINUX_MMC_CORE_H
|
||||
|
||||
#include <linux/completion.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct mmc_data;
|
||||
struct mmc_request;
|
||||
|
||||
#define UHS2_MAX_PAYLOAD_LEN 2
|
||||
#define UHS2_MAX_RESP_LEN 20
|
||||
|
||||
struct uhs2_command {
|
||||
u16 header;
|
||||
u16 arg;
|
||||
__be32 payload[UHS2_MAX_PAYLOAD_LEN];
|
||||
u8 payload_len;
|
||||
u8 packet_len;
|
||||
u8 tmode_half_duplex;
|
||||
u8 uhs2_resp[UHS2_MAX_RESP_LEN]; /* UHS2 native cmd resp */
|
||||
u8 uhs2_resp_len; /* UHS2 native cmd resp len */
|
||||
};
|
||||
|
||||
struct mmc_command {
|
||||
u32 opcode;
|
||||
u32 arg;
|
||||
#define MMC_CMD23_ARG_REL_WR (1 << 31)
|
||||
#define MMC_CMD23_ARG_TAG_REQ (1 << 29)
|
||||
u32 resp[4];
|
||||
unsigned int flags; /* expected response type */
|
||||
#define MMC_RSP_PRESENT (1 << 0)
|
||||
#define MMC_RSP_136 (1 << 1) /* 136 bit response */
|
||||
#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
|
||||
#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
|
||||
#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
|
||||
|
||||
#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */
|
||||
#define MMC_CMD_AC (0 << 5)
|
||||
#define MMC_CMD_ADTC (1 << 5)
|
||||
#define MMC_CMD_BC (2 << 5)
|
||||
#define MMC_CMD_BCR (3 << 5)
|
||||
|
||||
#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */
|
||||
#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */
|
||||
#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */
|
||||
#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */
|
||||
|
||||
/*
|
||||
* These are the native response types, and correspond to valid bit
|
||||
* patterns of the above flags. One additional valid pattern
|
||||
* is all zeros, which means we don't expect a response.
|
||||
*/
|
||||
#define MMC_RSP_NONE (0)
|
||||
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
|
||||
#define MMC_RSP_R1B_NO_CRC (MMC_RSP_PRESENT|MMC_RSP_OPCODE|MMC_RSP_BUSY)
|
||||
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
|
||||
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
|
||||
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
|
||||
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
|
||||
#define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE))
|
||||
|
||||
/*
|
||||
* These are the SPI response types for MMC, SD, and SDIO cards.
|
||||
* Commands return R1, with maybe more info. Zero is an error type;
|
||||
* callers must always provide the appropriate MMC_RSP_SPI_Rx flags.
|
||||
*/
|
||||
#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1)
|
||||
#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY)
|
||||
#define MMC_RSP_SPI_R2 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2)
|
||||
#define MMC_RSP_SPI_R3 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4)
|
||||
#define MMC_RSP_SPI_R4 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4)
|
||||
#define MMC_RSP_SPI_R5 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2)
|
||||
#define MMC_RSP_SPI_R7 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4)
|
||||
|
||||
#define mmc_spi_resp_type(cmd) ((cmd)->flags & \
|
||||
(MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY|MMC_RSP_SPI_S2|MMC_RSP_SPI_B4))
|
||||
|
||||
/*
|
||||
* These are the command types.
|
||||
*/
|
||||
#define mmc_cmd_type(cmd) ((cmd)->flags & MMC_CMD_MASK)
|
||||
|
||||
unsigned int retries; /* max number of retries */
|
||||
int error; /* command error */
|
||||
|
||||
/*
|
||||
* Standard errno values are used for errors, but some have specific
|
||||
* meaning in the MMC layer:
|
||||
*
|
||||
* ETIMEDOUT Card took too long to respond
|
||||
* EILSEQ Basic format problem with the received or sent data
|
||||
* (e.g. CRC check failed, incorrect opcode in response
|
||||
* or bad end bit)
|
||||
* EINVAL Request cannot be performed because of restrictions
|
||||
* in hardware and/or the driver
|
||||
* ENOMEDIUM Host can determine that the slot is empty and is
|
||||
* actively failing requests
|
||||
*/
|
||||
|
||||
unsigned int busy_timeout; /* busy detect timeout in ms */
|
||||
struct mmc_data *data; /* data segment associated with cmd */
|
||||
struct mmc_request *mrq; /* associated request */
|
||||
|
||||
struct uhs2_command *uhs2_cmd; /* UHS2 command */
|
||||
|
||||
/* for SDUC */
|
||||
bool has_ext_addr;
|
||||
u8 ext_addr;
|
||||
};
|
||||
|
||||
struct mmc_data {
|
||||
unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */
|
||||
unsigned int timeout_clks; /* data timeout (in clocks) */
|
||||
unsigned int blksz; /* data block size */
|
||||
unsigned int blocks; /* number of blocks */
|
||||
unsigned int blk_addr; /* block address */
|
||||
int error; /* data error */
|
||||
unsigned int flags;
|
||||
|
||||
#define MMC_DATA_WRITE BIT(8)
|
||||
#define MMC_DATA_READ BIT(9)
|
||||
/* Extra flags used by CQE */
|
||||
#define MMC_DATA_QBR BIT(10) /* CQE queue barrier*/
|
||||
#define MMC_DATA_PRIO BIT(11) /* CQE high priority */
|
||||
#define MMC_DATA_REL_WR BIT(12) /* Reliable write */
|
||||
#define MMC_DATA_DAT_TAG BIT(13) /* Tag request */
|
||||
#define MMC_DATA_FORCED_PRG BIT(14) /* Forced programming */
|
||||
|
||||
unsigned int bytes_xfered;
|
||||
|
||||
struct mmc_command *stop; /* stop command */
|
||||
struct mmc_request *mrq; /* associated request */
|
||||
|
||||
unsigned int sg_len; /* size of scatter list */
|
||||
int sg_count; /* mapped sg entries */
|
||||
struct scatterlist *sg; /* I/O scatter list */
|
||||
s32 host_cookie; /* host private data */
|
||||
};
|
||||
|
||||
struct mmc_host;
|
||||
struct mmc_request {
|
||||
struct mmc_command *sbc; /* SET_BLOCK_COUNT for multiblock */
|
||||
struct mmc_command *cmd;
|
||||
struct mmc_data *data;
|
||||
struct mmc_command *stop;
|
||||
|
||||
struct completion completion;
|
||||
struct completion cmd_completion;
|
||||
void (*done)(struct mmc_request *);/* completion function */
|
||||
/*
|
||||
* Notify uppers layers (e.g. mmc block driver) that recovery is needed
|
||||
* due to an error associated with the mmc_request. Currently used only
|
||||
* by CQE.
|
||||
*/
|
||||
void (*recovery_notifier)(struct mmc_request *);
|
||||
struct mmc_host *host;
|
||||
|
||||
/* Allow other commands during this ongoing data transfer or busy wait */
|
||||
bool cap_cmd_during_tfr;
|
||||
|
||||
int tag;
|
||||
|
||||
#ifdef CONFIG_MMC_CRYPTO
|
||||
const struct bio_crypt_ctx *crypto_ctx;
|
||||
int crypto_key_slot;
|
||||
#endif
|
||||
struct uhs2_command uhs2_cmd;
|
||||
};
|
||||
|
||||
struct mmc_card;
|
||||
|
||||
void mmc_wait_for_req(struct mmc_host *host, struct mmc_request *mrq);
|
||||
int mmc_wait_for_cmd(struct mmc_host *host, struct mmc_command *cmd,
|
||||
int retries);
|
||||
|
||||
int mmc_hw_reset(struct mmc_card *card);
|
||||
int mmc_sw_reset(struct mmc_card *card);
|
||||
void mmc_set_data_timeout(struct mmc_data *data, const struct mmc_card *card);
|
||||
|
||||
#endif /* LINUX_MMC_CORE_H */
|
||||
@@ -102,11 +102,12 @@ if [ ! -f "${HOST_BUILD}/bin/qmlcachegen" ] || [ ! -f "${HOST_BUILD}/bin/qmlaots
|
||||
touch "${QML_BUILD_DIR}/jsroot.qmltypes"
|
||||
fi
|
||||
cmake --build "${DECL_HOST}" --target qmlcachegen -j"${COOKBOOK_MAKE_JOBS}" 2>/dev/null || echo "qmlcachegen skipped"
|
||||
# Fix qmlcachegen RPATH so it loads host Qt6 libs, not cross-compiled sysroot ones
|
||||
if [ -f "${DECL_HOST}/libexec/qmlcachegen" ]; then
|
||||
patchelf --set-rpath '$ORIGIN/../lib:$ORIGIN/../../qt-host-build/lib' \
|
||||
"${DECL_HOST}/libexec/qmlcachegen" 2>/dev/null || true
|
||||
fi
|
||||
for qt_tool in "${DECL_HOST}/libexec/qmlcachegen" "${DECL_HOST}/bin/qmlcachegen"; do
|
||||
if [ -f "${qt_tool}" ]; then
|
||||
patchelf --force-rpath --set-rpath '$ORIGIN/../lib:$ORIGIN/../../qt-host-build/lib' \
|
||||
"${qt_tool}" 2>/dev/null || true
|
||||
fi
|
||||
done
|
||||
|
||||
mkdir -p "${HOST_BUILD}/bin" "${HOST_BUILD}/libexec" "${HOST_BUILD}/lib/cmake"
|
||||
for tool in qmlcachegen qmllint qmlimportscanner qmltyperegistrar qmlaotstats svgtoqml; do
|
||||
@@ -119,6 +120,14 @@ if [ ! -f "${HOST_BUILD}/bin/qmlcachegen" ] || [ ! -f "${HOST_BUILD}/bin/qmlaots
|
||||
cp -a "${DECL_HOST}/tools/${tool}" "${HOST_BUILD}/bin/"
|
||||
fi
|
||||
done
|
||||
for qt_tool in "${HOST_BUILD}/bin/qmlcachegen" "${HOST_BUILD}/libexec/qmlcachegen" \
|
||||
"${HOST_BUILD}/bin/qmltyperegistrar" "${HOST_BUILD}/libexec/qmltyperegistrar" \
|
||||
"${HOST_BUILD}/bin/svgtoqml" "${HOST_BUILD}/libexec/svgtoqml"; do
|
||||
if [ -f "${qt_tool}" ]; then
|
||||
patchelf --force-rpath --set-rpath '$ORIGIN/../lib:$ORIGIN/../../lib' \
|
||||
"${qt_tool}" 2>/dev/null || true
|
||||
fi
|
||||
done
|
||||
cp -a "${DECL_HOST}/lib/cmake/Qt6QmlTools" "${HOST_BUILD}/lib/cmake/" 2>/dev/null || true
|
||||
cp -a "${DECL_HOST}/lib/cmake/Qt6QmlCompiler" "${HOST_BUILD}/lib/cmake/" 2>/dev/null || true
|
||||
cp -a "${DECL_HOST}/lib/cmake/Qt6QuickTools" "${HOST_BUILD}/lib/cmake/" 2>/dev/null || true
|
||||
@@ -178,26 +187,10 @@ fi
|
||||
python - <<'PY'
|
||||
import os
|
||||
from pathlib import Path
|
||||
|
||||
root = Path(os.environ["COOKBOOK_SOURCE"])
|
||||
|
||||
# Patch 1: Remove TARGET Qt::qsb condition from quickvectorimage
|
||||
src_cml = root / "src/CMakeLists.txt"
|
||||
text = src_cml.read_text()
|
||||
text = text.replace(
|
||||
'if(TARGET Qt::Gui AND TARGET Qt::qsb AND QT_FEATURE_qml_animation)',
|
||||
'if(TARGET Qt::Gui AND QT_FEATURE_qml_animation)')
|
||||
src_cml.write_text(text)
|
||||
|
||||
# Patch 2: Remove Network from find_package OPTIONAL_COMPONENTS
|
||||
# Qt6NetworkConfig.cmake:199 qt_make_features_available enters infinite
|
||||
# recursion with Qt6Config.cmake:256 when cross-compiling with
|
||||
# feature overrides. Removing Network from the component list avoids
|
||||
# loading Qt6NetworkConfig.cmake entirely.
|
||||
root_cml = root / "CMakeLists.txt"
|
||||
text = root_cml.read_text()
|
||||
text = text.replace(' Network ', ' ')
|
||||
root_cml.write_text(text)
|
||||
path = Path(os.environ["COOKBOOK_SOURCE"]) / "src/CMakeLists.txt"
|
||||
text = path.read_text()
|
||||
text = text.replace('if(TARGET Qt::Gui AND TARGET Qt::qsb AND QT_FEATURE_qml_animation)', 'if(TARGET Qt::Gui AND QT_FEATURE_qml_animation)')
|
||||
path.write_text(text)
|
||||
PY
|
||||
|
||||
cat > "${COOKBOOK_BUILD}/shader_stub.cmake" << 'EOFCMAKE'
|
||||
@@ -207,8 +200,10 @@ function(qt_internal_add_shader_helpers target name)
|
||||
endfunction()
|
||||
EOFCMAKE
|
||||
|
||||
HOST_QT6_LIBS="${DECL_HOST}/lib:${HOST_BUILD}/lib"
|
||||
export LD_LIBRARY_PATH="${HOST_QT6_LIBS}:${LD_LIBRARY_PATH:-}"
|
||||
|
||||
cmake "${COOKBOOK_SOURCE}" \
|
||||
-G Ninja \
|
||||
-C "${COOKBOOK_BUILD}/shader_stub.cmake" \
|
||||
-DCMAKE_TOOLCHAIN_FILE="${COOKBOOK_ROOT}/local/recipes/qt/redox-toolchain.cmake" \
|
||||
-DQT_HOST_PATH="${HOST_BUILD}" \
|
||||
@@ -218,11 +213,20 @@ cmake "${COOKBOOK_SOURCE}" \
|
||||
-DQt6ShaderToolsTools_DIR="${HOST_BUILD}/lib/cmake/Qt6ShaderToolsTools" \
|
||||
-DQT_BUILD_EXAMPLES=OFF \
|
||||
-DQT_BUILD_TESTS=OFF \
|
||||
-DQT_GENERATE_SBOM=OFF \
|
||||
-DQT_GENERATE_SBOM=OFF \
|
||||
-DQT_FEATURE_qml_jit=OFF \
|
||||
-DQT_FEATURE_ssl=OFF \
|
||||
-DQT_FEATURE_network=OFF \
|
||||
-DQT_FEATURE_localserver=OFF \
|
||||
-DQT_FEATURE_http=OFF \
|
||||
-DQT_FEATURE_udpsocket=OFF \
|
||||
-DQT_FEATURE_dnslookup=OFF \
|
||||
-DQT_FEATURE_networkinterface=OFF \
|
||||
-DQT_FEATURE_networkproxy=OFF \
|
||||
-DQT_FEATURE_socks5=OFF \
|
||||
-DQT_FEATURE_networkdiskcache=OFF \
|
||||
-Wno-dev
|
||||
|
||||
HOST_QT6_LIBS="${DECL_HOST}/lib:${HOST_BUILD}/lib"
|
||||
export LD_LIBRARY_PATH="${HOST_QT6_LIBS}:${LD_LIBRARY_PATH:-}"
|
||||
cmake --build . --target Qml Quick QuickWidgets QmlModels QmlWorkerScript QmlIntegration LabsSettings QuickControls2 QuickTemplates2 QuickVectorImageGeneratorPrivate QuickVectorImage QuickVectorImageHelpers -j${COOKBOOK_MAKE_JOBS}
|
||||
cmake --build . -j${COOKBOOK_MAKE_JOBS} 2>/dev/null || echo "Some targets failed (tools/qml expected)"
|
||||
|
||||
@@ -276,7 +280,6 @@ redbear_qt_rewrite_stage_build_paths "${STAGE_USR}" "${BUILD_DIR}"
|
||||
redbear_qt_rewrite_stage_include_paths "${STAGE_CMAKE_DIR}" "${SYSROOT}"
|
||||
redbear_qt_rewrite_stage_lib_paths "${STAGE_CMAKE_DIR}" "${SYSROOT}"
|
||||
redbear_qt_rewrite_stage_source_metatype_paths "${STAGE_CMAKE_DIR}" "${SYSROOT}" "${COOKBOOK_SOURCE}"
|
||||
redbear_qt_resolve_forwarding_headers "${STAGE_USR}" "${BUILD_DIR}"
|
||||
redbear_qt_copy_common_stage_to_sysroot "${STAGE_USR}" "${SYSROOT}"
|
||||
redbear_qt_copy_stage_qt6_cmake_to_sysroot "${STAGE_USR}" "${SYSROOT}"
|
||||
redbear_qt_copy_optional_stage_dir_to_sysroot "${STAGE_USR}" "${SYSROOT}" metatypes
|
||||
|
||||
@@ -20,7 +20,7 @@ find_package(Qt6 ${PROJECT_VERSION} CONFIG REQUIRED COMPONENTS BuildInternals)
|
||||
qt_internal_project_setup()
|
||||
|
||||
find_package(Qt6 ${PROJECT_VERSION} CONFIG REQUIRED Core)
|
||||
find_package(Qt6 ${PROJECT_VERSION} QUIET CONFIG OPTIONAL_COMPONENTS Gui Widgets OpenGL OpenGLWidgets Sql Concurrent Test TestInternalsPrivate LanguageServerPrivate Svg)
|
||||
find_package(Qt6 ${PROJECT_VERSION} QUIET CONFIG OPTIONAL_COMPONENTS Network Gui Widgets OpenGL OpenGLWidgets Sql Concurrent Test TestInternalsPrivate LanguageServerPrivate Svg)
|
||||
|
||||
# Set up QT_HOST_PATH as an extra root path to look for the ShaderToolsTools package
|
||||
# when cross-compiling.
|
||||
|
||||
@@ -1019,10 +1019,13 @@ pub fn render_process_panel<'a>(app: &'a App, focused: bool) -> Paragraph<'a> {
|
||||
.wrap(Wrap { trim: true })
|
||||
}
|
||||
|
||||
/// Build a tree prefix string for a process: `└─ ` (last child),
|
||||
/// `├─ ` (non-last child), or empty (root). Walks the ppid chain to
|
||||
/// determine depth and uses the next row in `all` to decide whether
|
||||
/// this row is the last sibling of its parent.
|
||||
/// Build a tree prefix string for a process. htop-style vertical
|
||||
/// bars: each ancestor level renders either `│ ` (the path
|
||||
/// continues below) or ` ` (the path is the last child of its
|
||||
/// ancestor). The row itself renders `└─ ` (last child) or `├─ `
|
||||
/// (non-last child), or no connector for roots. Walks the ppid
|
||||
/// chain to determine depth and uses the next row in `all` to
|
||||
/// decide whether each ancestor has a continuation below.
|
||||
///
|
||||
/// O(N) per call, O(N^2) worst case for the full render. Fine for
|
||||
/// the truncated top-50 list.
|
||||
@@ -1040,9 +1043,11 @@ fn tree_prefix(
|
||||
all.iter().map(|p| (p.pid, p)).collect();
|
||||
|
||||
// Walk up the ppid chain. Each step means this row is one level
|
||||
// deeper than its parent. Stop when we hit a root (ppid==0 or
|
||||
// ppid not in list) or a cycle (safety bound of 64 hops).
|
||||
let mut depth: usize = 0;
|
||||
// deeper than its parent. Record the chain of ancestors (from
|
||||
// parent up to root) for the bar-continuation check below.
|
||||
// Stop when we hit a root (ppid==0 or ppid not in list) or a
|
||||
// cycle (safety bound of 64 hops).
|
||||
let mut ancestors: Vec<u32> = Vec::new();
|
||||
let mut cur = pid;
|
||||
let max_walk = 64;
|
||||
for _ in 0..max_walk {
|
||||
@@ -1053,12 +1058,65 @@ fn tree_prefix(
|
||||
if p.ppid == 0 || !by_pid.contains_key(&p.ppid) {
|
||||
break;
|
||||
}
|
||||
ancestors.push(p.ppid);
|
||||
cur = p.ppid;
|
||||
depth += 1;
|
||||
}
|
||||
let depth = ancestors.len();
|
||||
|
||||
// "Last child" of immediate parent: this row is last iff the
|
||||
// next row in the list has a different ppid (or there is no
|
||||
// next row).
|
||||
let my_index = match all.iter().position(|p| p.pid == pid) {
|
||||
Some(i) => i,
|
||||
None => return String::new(),
|
||||
};
|
||||
let next_ppid = all.get(my_index + 1).map(|n| n.ppid);
|
||||
let is_last = next_ppid.map_or(true, |np| np != ppid);
|
||||
|
||||
// For each ancestor level, decide if the bar continues:
|
||||
// the bar at depth `d` (counting from 0 for the row itself's
|
||||
// parent) continues iff there is a next row whose ancestor
|
||||
// chain at that depth is the same ancestor. Equivalently: for
|
||||
// ancestor `a` at chain index `d`, look at the next row in
|
||||
// the list. If the next row's ancestor at depth `d` is
|
||||
// `a` (or the next row's ppid is `a`), then the bar at depth
|
||||
// `d` continues.
|
||||
let mut bar = String::new();
|
||||
for (d, &ancestor) in ancestors.iter().enumerate() {
|
||||
let next_row = all.get(my_index + 1);
|
||||
// Is the ancestor still "active" at this depth for the
|
||||
// NEXT row? An ancestor is active for the next row iff:
|
||||
// - the next row's ppid chain has `ancestor` at depth `d`,
|
||||
// OR
|
||||
// - the next row's ppid IS `ancestor` (the next row is
|
||||
// a child of the ancestor, so the ancestor is the
|
||||
// immediate parent of the next row).
|
||||
let ancestor_active_in_next = next_row.map_or(false, |n| {
|
||||
if n.ppid == ancestor {
|
||||
return true;
|
||||
}
|
||||
// Walk the next row's ancestor chain and see if
|
||||
// `ancestor` appears at the same depth.
|
||||
let mut next_cur = n.pid;
|
||||
for next_d in 0..=d {
|
||||
let np = match by_pid.get(&next_cur) {
|
||||
Some(np) => *np,
|
||||
None => return false,
|
||||
};
|
||||
if next_d == d {
|
||||
return np.ppid == ancestor;
|
||||
}
|
||||
if np.ppid == 0 || !by_pid.contains_key(&np.ppid) {
|
||||
return false;
|
||||
}
|
||||
next_cur = np.ppid;
|
||||
}
|
||||
false
|
||||
});
|
||||
bar.push_str(if ancestor_active_in_next { "│ " } else { " " });
|
||||
}
|
||||
|
||||
// Detect "this row has children in the visible list" — used to
|
||||
// show the fold/unfold indicator.
|
||||
// Fold/unfold marker.
|
||||
let has_children = all.iter().any(|p| p.ppid == pid);
|
||||
let is_folded = folded.contains(&pid);
|
||||
let fold_marker = if has_children {
|
||||
@@ -1069,26 +1127,11 @@ fn tree_prefix(
|
||||
|
||||
if depth == 0 {
|
||||
// Root: no connector, just the fold marker.
|
||||
return fold_marker.to_string();
|
||||
return format!("{}{}", bar, fold_marker);
|
||||
}
|
||||
|
||||
// "Last child" iff the next row in the list has a different
|
||||
// ppid (or there is no next row). Filter is applied at render
|
||||
// time but the sort_tree output is the source of truth for
|
||||
// sibling order, so this approximation is exact for unfiltered
|
||||
// rows.
|
||||
let my_index = match all.iter().position(|p| p.pid == pid) {
|
||||
Some(i) => i,
|
||||
None => return String::new(),
|
||||
};
|
||||
let is_last = match all.get(my_index + 1) {
|
||||
Some(next) => next.ppid != ppid,
|
||||
None => true,
|
||||
};
|
||||
|
||||
let indent = " ".repeat(depth - 1);
|
||||
let connector = if is_last { "└─ " } else { "├─ " };
|
||||
format!("{}{}{}", indent, connector, fold_marker)
|
||||
format!("{}{}{}", bar, connector, fold_marker)
|
||||
}
|
||||
|
||||
pub fn render_pid_detail(detail: &crate::pid_detail::PidDetail, pid: u32) -> Paragraph<'static> {
|
||||
|
||||
Reference in New Issue
Block a user