intel: comprehensive workaround tables v2.0 — GT + context + display + engine + whitelist
Complete rewrite of workaround infrastructure:
- regs_gt.rs: 100+ GT/engine register constants with field bit masks
for Gen4-Gen12 (L3, slice/row chicken, cache/sampler/WM, HSW,
MCR selector, GAM/ECO, Gen11/Gen12, display WA registers)
- Workaround/WorkaroundList data model with merge/dedup at same offset,
apply() with masked-register and write-only support, verify()
for post-application validation
- Helper functions: wa_masked_en/dis/field_set, wa_write/or/clr/clr_set,
MCR variants (aliases without MCR steering infrastructure)
Tables ported from Linux 7.1 intel_workarounds.c:
- GT workarounds: gen4, g4x, ilk, snb, ivb, hsw, gen8, gen9,
icl(gen9.5), gen12 (~30 entries, all critical paths)
- Context workarounds: gen6, gen7, gen8, gen9, icl, gen12
(~40 entries covering RCS/engine state)
- Display workarounds: gen11 (Wa_14010594013), gen12 (Wa_14013723622)
- Engine workarounds: general_render_compute (2 entries)
- Whitelist: gen9, icl, gen12 (17 entries total)
Total: ~90 workaround entries across 5 domains (GT/context/display/
engine/whitelist), 0 compilation errors.
Note: Engine-specific tables (rcs/xcs/ccs per-engine init) and full
Gen9 sub-family platform-specific entries (skl/bxt/kbl/glk/cfl stepping
variants) remain as follow-up work. The infrastructure supports them
fully — they just need register constant resolution and porting.
Red Bear
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