intel: CX0 PHY for Xe2 + display.rs documentation
cx0_phy.rs (130 lines): Xe2 unified display PHY
Arrow Lake / Lunar Lake / Battlemage physical layer
CX0 PLL sharing: one PLL drives multiple lanes at 20 Gbps
DP 2.1 UHBR20, HDMI 2.1 FRL, eDP mode support
Per-lane calibration: voltage swing, pre-emphasis, CTLE
PLL lock + PHY ready + lane calibration timeout sequences
display.rs: module header documentation
DDI modeset flow: pipe detection → connector enumeration → EDID read
EDID fallback chain: DP AUX → GMBUS → synthetic 1920x1080
Mode timing: HTOTAL/HBLANK/HSYNC/VTOTAL/VBLANK/VSYNC programming
Ported from Linux 7.1:
intel_cx0_phy.c → Cx0Phy
Intel driver: 92 files, 0 errors
vasilito
0d17751971