Improve readability
This commit is contained in:
+6
-4
@@ -120,6 +120,8 @@ const BASE_GDT: [GdtEntry; 9] = [
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GdtEntry::new(0, 0, GDT_A_PRESENT | GDT_A_RING_3 | GDT_A_TSS_AVAIL, 0),
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];
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const IOBITMAP_SIZE: usize = 8192;
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#[repr(C, align(4096))]
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pub struct ProcessorControlRegion {
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pub self_ref: usize,
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@@ -127,8 +129,8 @@ pub struct ProcessorControlRegion {
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pub gdt: [GdtEntry; 9],
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percpu: crate::percpu::PercpuBlock,
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pub tss: TssWrapper,
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pub pio_bitmap: [u8; 8192],
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pub all_ones: u8,
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pub _pio_bitmap: [u8; IOBITMAP_SIZE],
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pub _all_ones: u8,
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}
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// NOTE: Despite not using #[repr(packed)], we do know that while there may be some padding
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@@ -193,12 +195,12 @@ pub unsafe fn init_paging(stack_offset: usize, cpu_id: LogicalCpuId) {
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};
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{
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pcr.all_ones = 0xFF;
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pcr._all_ones = 0xFF;
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pcr.tss.0.iobp_offset = 0xFFFF;
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let tss = &pcr.tss.0 as *const _ as usize as u32;
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pcr.gdt[GDT_TSS].set_offset(tss);
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pcr.gdt[GDT_TSS].set_limit(mem::size_of::<TaskStateSegment>() as u32 + 8192);
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pcr.gdt[GDT_TSS].set_limit(mem::size_of::<TaskStateSegment>() as u32 + IOBITMAP_SIZE);
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}
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// Load the new GDT, which is correctly located in thread local storage.
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@@ -121,8 +121,12 @@ pub struct ProcessorControlRegion {
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pub gdt: [GdtEntry; 8],
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pub percpu: PercpuBlock,
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pub tss: TaskStateSegment,
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pub iobitmap: [u8; IOBITMAP_SIZE as usize],
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pub all_ones: u8,
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// These two fields are read by the CPU, but not currently modified by the kernel. Instead, the
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// kernel sets the `iomap_base` field in the TSS, to either point to this bitmap, or outside
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// the TSS, in which case userspace is not granted port IO access.
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pub _iobitmap: [u8; IOBITMAP_SIZE as usize],
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pub _all_ones: u8,
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}
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const _: () = {
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@@ -213,7 +217,7 @@ pub unsafe fn init_paging(stack_offset: usize, cpu_id: LogicalCpuId) {
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{
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pcr.tss.iomap_base = 0xFFFF;
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pcr.all_ones = 0xFF;
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pcr._all_ones = 0xFF;
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let tss = &mut pcr.tss as *mut TaskStateSegment as usize as u64;
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let tss_lo = (tss & 0xFFFF_FFFF) as u32;
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