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Merge branch 'ihdgd_cleanup' into 'main'

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drivers/graphics/ihdgd: Fix a bunch of warnings

See merge request redox-os/base!73
This commit is contained in:
Jeremy Soller
2025-12-18 12:17:42 -07:00
parent 0fee261866 2422b3860c
commit ebf3680dae
5 changed files with 29 additions and 25 deletions
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drivers/graphics/ihdgd/src/device/ddi.rs
+7 -7
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@@ -2,7 +2,7 @@ use common::io::{Io, MmioPtr, WriteOnly};
use std::sync::Arc;
use syscall::error::{Error, Result, EIO};
use super::{DeviceKind, GpioPort, MmioRegion};
use super::{GpioPort, MmioRegion};
// IHD-OS-TGL-Vol 2c-12.21 DDI_AUX_CTL
pub const DDI_AUX_CTL_BUSY: u32 = 1 << 31;
@@ -262,7 +262,7 @@ impl Ddi {
// Clear cmnkeeper_enable for HDMI
{
// It is not possible to read from GRP register, so use LN0 as template
let mut pcs_dw1_ln0 = self.port_pcs(PortPcsReg::Dw1, PortLane::Ln0).unwrap();
let pcs_dw1_ln0 = self.port_pcs(PortPcsReg::Dw1, PortLane::Ln0).unwrap();
let mut pcs_dw1_grp =
WriteOnly::new(self.port_pcs(PortPcsReg::Dw1, PortLane::Grp).unwrap());
let mut v = pcs_dw1_ln0.read();
@@ -293,7 +293,7 @@ impl Ddi {
}
// Clear training enable to change swing values
let mut tx_dw5_ln0 = self.port_tx(PortTxReg::Dw5, PortLane::Ln0).unwrap();
let tx_dw5_ln0 = self.port_tx(PortTxReg::Dw5, PortLane::Ln0).unwrap();
let mut tx_dw5_grp = WriteOnly::new(self.port_tx(PortTxReg::Dw5, PortLane::Grp).unwrap());
{
let mut v = tx_dw5_ln0.read();
@@ -324,10 +324,10 @@ impl Ddi {
| PORT_TX_DW5_COEFF_POLARITY
| PORT_TX_DW5_SCALING_MODE_SEL_MASK
| PORT_TX_DW5_RTERM_SELECT_MASK);
v |= ((setting.dw5_2_tap_disable << PORT_TX_DW5_DISABLE_2_TAP_SHIFT)
v |= (setting.dw5_2_tap_disable << PORT_TX_DW5_DISABLE_2_TAP_SHIFT)
| PORT_TX_DW5_DISABLE_3_TAP
| (0b010 << PORT_TX_DW5_SCALING_MODE_SEL_SHIFT)
| (0b110 << PORT_TX_DW5_RTERM_SELECT_SHIFT));
| (0b110 << PORT_TX_DW5_RTERM_SELECT_SHIFT);
tx_dw5_grp.write(v);
}
@@ -344,9 +344,9 @@ impl Ddi {
v &= !(PORT_TX_DW2_SWING_SEL_UPPER_MASK
| PORT_TX_DW2_SWING_SEL_LOWER_MASK
| PORT_TX_DW2_RCOMP_SCALAR_MASK);
v |= ((((setting.dw2_swing_sel >> 3) & 1) << PORT_TX_DW2_SWING_SEL_UPPER_SHIFT)
v |= (((setting.dw2_swing_sel >> 3) & 1) << PORT_TX_DW2_SWING_SEL_UPPER_SHIFT)
| ((setting.dw2_swing_sel & 0b111) << PORT_TX_DW2_SWING_SEL_LOWER_SHIFT)
| (0x98 << PORT_TX_DW2_RCOMP_SCALAR_SHIFT));
| (0x98 << PORT_TX_DW2_RCOMP_SCALAR_SHIFT);
tx_dw2.write(v);
}
drivers/graphics/ihdgd/src/device/dpll.rs
+2 -2
View File
@@ -1,7 +1,7 @@
use common::io::{Io, MmioPtr};
use syscall::error::{Error, Result, EIO};
use super::{DeviceKind, MmioRegion};
use super::MmioRegion;
pub const DPLL_CFGCR1_QDIV_RATIO_SHIFT: u32 = 10;
pub const DPLL_CFGCR1_QDIV_RATIO_MASK: u32 = 0xFF << DPLL_CFGCR1_QDIV_RATIO_SHIFT;
@@ -150,7 +150,7 @@ impl Dpll {
| DPLL_CFGCR1_KDIV_MASK
| DPLL_CFGCR1_PDIV_MASK;
v &= !mask;
v |= (setting.cfgcr1 & mask);
v |= setting.cfgcr1 & mask;
self.cfgcr1.write(v);
}
drivers/graphics/ihdgd/src/device/gpio.rs
+15 -10
View File
@@ -1,8 +1,7 @@
use std::convert::Infallible;
use common::io::{Io, MmioPtr};
use embedded_hal::{
blocking::i2c::{self, Operation, SevenBitAddress},
digital,
};
use embedded_hal::digital::v2 as digital;
use super::MmioRegion;
@@ -57,25 +56,31 @@ pub struct GpioPin {
}
impl digital::InputPin for GpioPin {
fn is_high(&self) -> bool {
((self.ctl.read() >> self.shift) & GPIO_VAL_IN) == GPIO_VAL_IN
type Error = Infallible;
fn is_high(&self) -> Result<bool, Infallible> {
Ok(((self.ctl.read() >> self.shift) & GPIO_VAL_IN) == GPIO_VAL_IN)
}
fn is_low(&self) -> bool {
((self.ctl.read() >> self.shift) & GPIO_VAL_IN) == 0
fn is_low(&self) -> Result<bool, Infallible> {
Ok(((self.ctl.read() >> self.shift) & GPIO_VAL_IN) == 0)
}
}
impl digital::OutputPin for GpioPin {
fn set_low(&mut self) {
type Error = Infallible;
fn set_low(&mut self) -> Result<(), Infallible> {
// Set GPIO to output with value 0
let value = GPIO_DIR_MASK | GPIO_DIR_OUT | GPIO_VAL_MASK;
self.ctl.write(value << self.shift);
Ok(())
}
fn set_high(&mut self) {
fn set_high(&mut self) -> Result<(), Infallible> {
// Assuming external pull-up, set GPIO to input
let value = GPIO_DIR_MASK;
self.ctl.write(value << self.shift);
Ok(())
}
}
drivers/graphics/ihdgd/src/device/mod.rs
+5 -5
View File
@@ -5,7 +5,7 @@ use common::{
use embedded_hal::prelude::*;
use pcid_interface::PciFunction;
use range_alloc::RangeAllocator;
use std::{collections::VecDeque, mem, ptr, sync::Arc, time::Duration};
use std::{collections::VecDeque, mem, sync::Arc, time::Duration};
use syscall::error::{Error, Result, EIO, ENODEV, ERANGE};
mod aux;
@@ -569,7 +569,7 @@ impl Device {
Ok(edid_data)
};
let mut gpio_read_edid = |ddi: &mut Ddi| -> Result<[u8; 128]> {
let gpio_read_edid = |ddi: &mut Ddi| -> Result<[u8; 128]> {
let Some(port) = &ddi.gpio_port else {
return Err(Error::new(EIO));
};
@@ -728,7 +728,7 @@ impl Device {
let mut v = dpclka_cfgcr0.read();
v &= !(DPCLKA_CFGCR0_CLOCK_MASK << clock_shift);
v |= (dpll.dpclka_cfgcr0_clock_value << clock_shift);
v |= dpll.dpclka_cfgcr0_clock_value << clock_shift;
dpclka_cfgcr0.write(v);
}
@@ -890,7 +890,7 @@ impl Device {
TRANS_DDI_FUNC_CTL_PORT_WIDTH_4;
if let Some(transcoder_index) = ddi.transcoder_index {
ddi_func_ctl |= (transcoder_index << transcoder.ddi_func_ctl_ddi_shift);
ddi_func_ctl |= transcoder_index << transcoder.ddi_func_ctl_ddi_shift;
}
match input {
@@ -1082,7 +1082,7 @@ impl Device {
match event {
Event::DdiHotplug(ddi_name) => {
log::info!("DDI {} plugged", ddi_name);
for attempt in 0..4 {
for _attempt in 0..4 {
//TODO: gmbus times out!
match self.probe_ddi(ddi_name) {
Ok(true) => {
drivers/graphics/ihdgd/src/main.rs
-1
View File
@@ -2,7 +2,6 @@ use driver_graphics::GraphicsScheme;
use event::{user_data, EventQueue};
use inputd::DisplayHandle;
use pcid_interface::{irq_helpers::pci_allocate_interrupt_vector, PciFunctionHandle};
use redox_scheme::{RequestKind, SignalBehavior, Socket};
use std::{
io::{Read, Write},
os::fd::AsRawFd,