Support detecting USB port speeds.

This commit is contained in:
4lDO2
2020-02-10 16:23:19 +01:00
parent cff3cf0d28
commit e052c5968d
8 changed files with 415 additions and 57 deletions
Generated
+35 -35
View File
@@ -6,7 +6,7 @@ version = "0.1.0"
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+1 -1
View File
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redox_event = { git = "https://gitlab.redox-os.org/redox-os/event.git" }
redox_syscall = { git = "https://gitlab.redox-os.org/4lDO2/syscall.git", branch = "dma-slices" }
redox_syscall = { git = "https://gitlab.redox-os.org/redox-os/syscall.git" }
serde = { version = "1", features = ["derive"] }
serde_json = "1"
smallvec = { version = "1", features = ["serde"] }
+16
View File
@@ -16,10 +16,17 @@ pub struct CapabilityRegs {
pub const HCC_PARAMS1_MAXPSASIZE_MASK: u32 = 0xF000; // 15:12
pub const HCC_PARAMS1_MAXPSASIZE_SHIFT: u8 = 12;
pub const HCC_PARAMS1_XECP_MASK: u32 = 0xFFFF_0000;
pub const HCC_PARAMS1_XECP_SHIFT: u8 = 16;
pub const HCC_PARAMS2_LEC_BIT: u32 = 1 << 4;
pub const HCC_PARAMS2_CIC_BIT: u32 = 1 << 5;
pub const HCS_PARAMS1_MAX_PORTS_MASK: u32 = 0xFF00_0000;
pub const HCS_PARAMS1_MAX_PORTS_SHIFT: u8 = 24;
pub const HCS_PARAMS1_MAX_SLOTS_MASK: u32 = 0x0000_00FF;
pub const HCS_PARAMS1_MAX_SLOTS_SHIFT: u8 = 0;
impl CapabilityRegs {
pub fn lec(&self) -> bool {
self.hcc_params2.readf(HCC_PARAMS2_LEC_BIT)
@@ -31,4 +38,13 @@ impl CapabilityRegs {
((self.hcc_params1.read() & HCC_PARAMS1_MAXPSASIZE_MASK) >> HCC_PARAMS1_MAXPSASIZE_SHIFT)
as u8
}
pub fn max_ports(&self) -> u8 {
((self.hcs_params1.read() & HCS_PARAMS1_MAX_PORTS_MASK) >> HCS_PARAMS1_MAX_PORTS_SHIFT) as u8
}
pub fn max_slots(&self) -> u8 {
(self.hcs_params1.read() & HCS_PARAMS1_MAX_SLOTS_MASK) as u8
}
pub fn ext_caps_ptr_in_dwords(&self) -> u16 {
((self.hcc_params1.read() & HCC_PARAMS1_XECP_MASK) >> HCC_PARAMS1_XECP_SHIFT) as u16
}
}
+242 -2
View File
@@ -1,4 +1,54 @@
use syscall::Mmio;
use std::ops::Range;
use std::ptr::NonNull;
use std::{fmt, mem, ptr, slice};
use syscall::{Io, Mmio};
pub struct ExtendedCapabilitiesIter {
base: *const u8,
}
impl ExtendedCapabilitiesIter {
pub unsafe fn new(base: *const u8) -> Self {
Self {
base,
}
}
}
impl Iterator for ExtendedCapabilitiesIter {
type Item = (NonNull<u8>, u8); // pointer, capability id
fn next(&mut self) -> Option<Self::Item> {
unsafe {
let current = NonNull::new(self.base as *mut _)?;
let reg = current.cast::<Mmio<u32>>().as_ref().read();
let capability_id = (reg & 0xFF) as u8;
let next_rel_in_dwords = ((reg & 0xFF00) >> 8) as u8;
let next_rel = u16::from(next_rel_in_dwords) << 2;
self.base = if next_rel != 0 { self.base.offset(next_rel as isize) } else { ptr::null() };
Some((current, capability_id))
}
}
}
#[repr(u8)]
pub enum CapabilityId {
// bit 0 is reserved
UsbLegacySupport = 1,
SupportedProtocol,
ExtendedPowerManagement,
IoVirtualization,
MessageInterrupt,
LocalMem,
// bits 7-9 are reserved
UsbDebugCapability = 10,
// bits 11-16 are reserved
ExtendedMessageInterrupt = 17,
// bits 18-191 are reserved
// bits 192-255 are vendor-defined
}
#[repr(packed)]
pub struct SupportedProtoCap {
@@ -6,5 +56,195 @@ pub struct SupportedProtoCap {
b: Mmio<u32>,
c: Mmio<u32>,
d: Mmio<u32>,
protocols: [Mmio<u32>],
protocol_speeds: [u8; 0],
}
#[repr(packed)]
pub struct ProtocolSpeed {
a: Mmio<u32>,
}
pub const PROTO_SPEED_PSIV_MASK: u32 = 0x0000_000F;
pub const PROTO_SPEED_PSIV_SHIFT: u8 = 0;
pub const PROTO_SPEED_PSIE_MASK: u32 = 0x0000_0030;
pub const PROTO_SPEED_PSIE_SHIFT: u8 = 4;
pub const PROTO_SPEED_PLT_MASK: u32 = 0x0000_00C0;
pub const PROTO_SPEED_PLT_SHIFT: u8 = 6;
pub const PROTO_SPEED_PFD_BIT: u32 = 1 << PROTO_SPEED_PFD_SHIFT;
pub const PROTO_SPEED_PFD_SHIFT: u8 = 8;
pub const PROTO_SPEED_LP_MASK: u32 = 0x0000_C000;
pub const PROTO_SPEED_LP_SHIFT: u8 = 14;
pub const PROTO_SPEED_PSIM_MASK: u32 = 0xFFFF_0000;
pub const PROTO_SPEED_PSIM_SHIFT: u8 = 16;
#[repr(u8)]
#[derive(Clone, Copy, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)]
pub enum Psie {
Bps,
Kbps,
Mbps,
Gbps,
}
#[repr(u8)]
#[derive(Clone, Copy, Debug, Eq, Hash, PartialEq)]
pub enum Plt {
Symmetric,
Reserved,
AsymmetricRx,
AsymmetricTx,
}
#[repr(u8)]
#[derive(Clone, Copy, Debug, Eq, Hash, PartialEq)]
pub enum Lp {
SuperSpeed,
SuperSpeedPlus,
Rsvd2,
Rsvd3,
}
impl ProtocolSpeed {
pub const fn from_raw(raw: u32) -> Self {
Self {
a: Mmio::from(raw),
}
}
pub fn is_lowspeed(&self) -> bool {
self.psim() == 1500 && self.psie() == Psie::Kbps
}
pub fn is_fullspeed(&self) -> bool {
self.psim() == 12 && self.psie() == Psie::Mbps
}
pub fn is_highspeed(&self) -> bool {
self.psim() == 480 && self.psie() == Psie::Mbps
}
/// Protocol speed ID value
pub fn psiv(&self) -> u8 {
((self.a.read() & PROTO_SPEED_PSIV_MASK) >> PROTO_SPEED_PSIV_SHIFT) as u8
}
pub fn psie_raw(&self) -> u8 {
((self.a.read() & PROTO_SPEED_PSIE_MASK) >> PROTO_SPEED_PSIE_SHIFT) as u8
}
/// Protocol speed ID exponent
pub fn psie(&self) -> Psie {
// safe because psie_raw can only return values in 0..=3
unsafe { mem::transmute(self.psie_raw()) }
}
pub fn plt_raw(&self) -> u8 {
((self.a.read() & PROTO_SPEED_PLT_MASK) >> PROTO_SPEED_PLT_SHIFT) as u8
}
/// PSI type
pub fn plt(&self) -> Plt {
// safe because plt_raw can only return values in 0..=3
unsafe { mem::transmute(self.plt_raw()) }
}
/// PSI Full-duplex
pub fn pfd(&self) -> bool {
self.a.readf(PROTO_SPEED_PFD_BIT)
}
pub fn lp_raw(&self) -> u8 {
((self.a.read() & PROTO_SPEED_LP_MASK) >> PROTO_SPEED_LP_SHIFT) as u8
}
/// Link protocol
pub fn lp(&self) -> Lp {
// safe because lp_raw can only return values in 0..=3
unsafe { mem::transmute(self.lp_raw()) }
}
/// Protocol speed ID mantissa
pub fn psim(&self) -> u16 {
((self.a.read() & PROTO_SPEED_PSIM_MASK) >> PROTO_SPEED_PSIM_SHIFT) as u16
}
}
impl fmt::Debug for ProtocolSpeed {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
f.debug_struct("ProtocolSpeed")
.field("psiv", &self.psiv())
.field("psie", &self.psie())
.field("plt", &self.plt())
.field("pfd", &self.pfd())
.field("lp", &self.lp())
.field("psim", &self.psim())
.finish()
}
}
pub const SUPP_PROTO_CAP_REV_MIN_MASK: u32 = 0x00FF_0000;
pub const SUPP_PROTO_CAP_REV_MIN_SHIFT: u8 = 16;
pub const SUPP_PROTO_CAP_REV_MAJ_MASK: u32 = 0xFF00_0000;
pub const SUPP_PROTO_CAP_REV_MAJ_SHIFT: u8 = 24;
pub const SUPP_PROTO_CAP_COMPAT_PORT_OFF_MASK: u32 = 0x0000_00FF;
pub const SUPP_PROTO_CAP_COMPAT_PORT_OFF_SHIFT: u8 = 0;
pub const SUPP_PROTO_CAP_COMPAT_PORT_CNT_MASK: u32 = 0x0000_FF00;
pub const SUPP_PROTO_CAP_COMPAT_PORT_CNT_SHIFT: u8 = 8;
pub const SUPP_PROTO_CAP_PROTO_DEF_MASK: u32 = 0x0FFF_0000;
pub const SUPP_PROTO_CAP_PROTO_DEF_SHIFT: u8 = 16;
pub const SUPP_PROTO_CAP_PSIC_MASK: u32 = 0xF000_0000;
pub const SUPP_PROTO_CAP_PSIC_SHIFT: u8 = 28;
pub const SUPP_PROTO_CAP_PORT_SLOT_TYPE_MASK: u32 = 0x0000_001F;
pub const SUPP_PROTO_CAP_PORT_SLOT_TYPE_SHIFT: u8 = 0;
impl SupportedProtoCap {
pub unsafe fn protocol_speeds(&self) -> &[ProtocolSpeed] {
slice::from_raw_parts(&self.protocol_speeds as *const u8 as *const _, self.psic() as usize)
}
pub unsafe fn protocol_speeds_mut(&mut self) -> &mut [ProtocolSpeed] {
// XXX: Variance really is annoying sometimes.
slice::from_raw_parts_mut(&self.protocol_speeds as *const u8 as *mut u8 as *mut _, self.psic() as usize)
}
pub fn rev_minor(&self) -> u8 {
((self.a.read() & SUPP_PROTO_CAP_REV_MIN_MASK) >> SUPP_PROTO_CAP_REV_MIN_SHIFT) as u8
}
pub fn rev_major(&self) -> u8 {
((self.a.read() & SUPP_PROTO_CAP_REV_MAJ_MASK) >> SUPP_PROTO_CAP_REV_MAJ_SHIFT) as u8
}
pub fn name_string(&self) -> [u8; 4] {
// TODO: Little endian, right?
u32::to_le_bytes(self.b.read())
}
pub fn compat_port_offset(&self) -> u8 {
((self.c.read() & SUPP_PROTO_CAP_COMPAT_PORT_OFF_MASK) >> SUPP_PROTO_CAP_COMPAT_PORT_OFF_SHIFT) as u8
}
pub fn compat_port_count(&self) -> u8 {
((self.c.read() & SUPP_PROTO_CAP_COMPAT_PORT_CNT_MASK) >> SUPP_PROTO_CAP_COMPAT_PORT_CNT_SHIFT) as u8
}
pub fn compat_port_range(&self) -> Range<u8> {
self.compat_port_offset()..self.compat_port_offset() + self.compat_port_count()
}
pub fn proto_defined(&self) -> u16 {
((self.c.read() & SUPP_PROTO_CAP_PROTO_DEF_MASK) >> SUPP_PROTO_CAP_PROTO_DEF_SHIFT) as u16
}
pub fn psic(&self) -> u8 {
((self.c.read() & SUPP_PROTO_CAP_PSIC_MASK) >> SUPP_PROTO_CAP_PSIC_SHIFT) as u8
}
pub fn proto_slot_ty(&self) -> u8 {
((self.d.read() & SUPP_PROTO_CAP_PORT_SLOT_TYPE_MASK) >> SUPP_PROTO_CAP_PORT_SLOT_TYPE_SHIFT) as u8
}
}
impl fmt::Debug for SupportedProtoCap {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
f.debug_struct("SupportedProtoCap")
.field("rev_minor", &self.rev_minor())
.field("rev_major", &self.rev_major())
.field("name_string", &String::from_utf8_lossy(&self.name_string()))
.field("compat_port_offset", &self.compat_port_count())
.field("compat_port_count", &self.compat_port_offset())
.field("proto_defined", &self.proto_defined())
.field("psic", &self.psic())
.field("proto_slot_ty", &self.proto_slot_ty())
.field("proto_speeds", unsafe { &self.protocol_speeds().to_owned() })
.finish()
}
}
+108 -15
View File
@@ -1,6 +1,7 @@
use std::collections::BTreeMap;
use std::convert::TryFrom;
use std::pin::Pin;
use std::ptr::NonNull;
use std::sync::{atomic::AtomicBool, Arc, Mutex, Weak};
use std::{mem, process, slice, sync::atomic, task};
@@ -27,6 +28,7 @@ use self::capability::CapabilityRegs;
use self::command::CommandRing;
use self::context::{DeviceContextList, InputContext, StreamContextArray};
use self::doorbell::Doorbell;
use self::extended::{CapabilityId, ExtendedCapabilitiesIter, ProtocolSpeed, SupportedProtoCap};
use self::operational::OperationalRegs;
use self::port::Port;
use self::ring::Ring;
@@ -117,6 +119,8 @@ pub struct Xhci {
dev_ctx: DeviceContextList,
cmd: CommandRing,
base: *const u8,
handles: BTreeMap<usize, scheme::Handle>,
next_handle: usize,
port_states: BTreeMap<usize, PortState>,
@@ -169,10 +173,7 @@ impl Xhci {
let op = unsafe { &mut *(op_base as *mut OperationalRegs) };
println!(" - OP {:X}", op_base);
let max_slots;
let max_ports;
{
let (max_slots, max_ports) = {
println!(" - Wait for ready");
// Wait until controller is ready
while op.usb_sts.readf(1 << 11) {
@@ -196,13 +197,13 @@ impl Xhci {
}
println!(" - Read max slots");
// Read maximum slots and ports
let hcs_params1 = cap.hcs_params1.read();
max_slots = (hcs_params1 & 0xFF) as u8;
max_ports = ((hcs_params1 & 0xFF000000) >> 24) as u8;
let max_slots = cap.max_slots();
let max_ports = cap.max_ports();
println!(" - Max Slots: {}, Max Ports {}", max_slots, max_ports);
}
(max_slots, max_ports)
};
let port_base = op_base + 0x400;
let ports =
@@ -218,11 +219,12 @@ impl Xhci {
println!(" - RUNTIME {:X}", run_base);
let mut xhci = Xhci {
cap: cap,
op: op,
ports: ports,
dbs: dbs,
run: run,
base: address as *const u8,
cap,
op,
ports,
dbs,
run,
dev_ctx: DeviceContextList::new(max_slots)?,
cmd: CommandRing::new()?,
handles: BTreeMap::new(),
@@ -292,6 +294,10 @@ impl Xhci {
self.dbs[0].write(0);
println!(" - XHCI initialized");
for (pointer, capability) in self.capabilities_iter() {
dbg!(pointer, capability);
}
}
pub fn enable_port_slot(cmd: &mut CommandRing, dbs: &mut [Doorbell]) -> u8 {
@@ -345,7 +351,7 @@ impl Xhci {
{
input.add_context.write(1 << 1 | 1); // Enable the slot (zeroth bit) and the control endpoint (first bit).
input.device.slot.a.write((1 << 27) | (speed << 20)); // FIXME: The speed field, bits 23:20, is deprecated.
input.device.slot.a.write((1 << 27) | (u32::from(speed) << 20)); // FIXME: The speed field, bits 23:20, is deprecated.
input.device.slot.b.write(((i as u32 + 1) & 0xFF) << 16);
// control endpoint?
@@ -494,6 +500,93 @@ impl Xhci {
Ok(())
}
pub fn capabilities_iter(&self) -> ExtendedCapabilitiesIter {
unsafe { ExtendedCapabilitiesIter::new((self.base as *mut u8).offset((self.cap.ext_caps_ptr_in_dwords() << 2) as isize)) }
}
pub fn supported_protocols_iter(&self) -> impl Iterator<Item = &'static SupportedProtoCap> {
self.capabilities_iter().filter_map(|(pointer, cap_num)| unsafe {
if cap_num == CapabilityId::SupportedProtocol as u8 {
Some(&*pointer.cast::<SupportedProtoCap>().as_ptr())
} else {
None
}
})
}
pub fn supported_protocol_speeds(&self, port: u8) -> Option<impl Iterator<Item = &'static ProtocolSpeed>> {
use extended::*;
const DEFAULT_SUPP_PROTO_SPEEDS: [ProtocolSpeed; 7] = [
// Full-speed
ProtocolSpeed::from_raw(
(Plt::Symmetric as u32) << PROTO_SPEED_PLT_SHIFT
| (false as u32) << PROTO_SPEED_PFD_SHIFT
| (Psie::Mbps as u32) << PROTO_SPEED_PSIE_SHIFT
| 12 << PROTO_SPEED_PSIM_SHIFT
| 1 << PROTO_SPEED_PSIV_SHIFT
),
// Low-speed
ProtocolSpeed::from_raw(
(Plt::Symmetric as u32) << PROTO_SPEED_PLT_SHIFT
| (false as u32) << PROTO_SPEED_PFD_SHIFT
| (Psie::Kbps as u32) << PROTO_SPEED_PSIE_SHIFT
| 1500 << PROTO_SPEED_PSIM_SHIFT
| 2 << PROTO_SPEED_PSIV_SHIFT
),
// High-speed
ProtocolSpeed::from_raw(
(Plt::Symmetric as u32) << PROTO_SPEED_PLT_SHIFT
| (false as u32) << PROTO_SPEED_PFD_SHIFT
| (Psie::Mbps as u32) << PROTO_SPEED_PSIE_SHIFT
| 480 << PROTO_SPEED_PSIM_SHIFT
| 3 << PROTO_SPEED_PSIV_SHIFT
),
// SuperSpeed Gen1 x1
ProtocolSpeed::from_raw(
(Plt::Symmetric as u32) << PROTO_SPEED_PLT_SHIFT
| (true as u32) << PROTO_SPEED_PFD_SHIFT
| (Psie::Gbps as u32) << PROTO_SPEED_PSIE_SHIFT
| 5 << PROTO_SPEED_PSIM_SHIFT
| (Lp::SuperSpeed as u32) << PROTO_SPEED_LP_SHIFT
| 4 << PROTO_SPEED_PSIV_SHIFT
),
// SuperSpeedPlus Gen2 x1
ProtocolSpeed::from_raw(
(Plt::Symmetric as u32) << PROTO_SPEED_PLT_SHIFT
| (true as u32) << PROTO_SPEED_PFD_SHIFT
| (Psie::Gbps as u32) << PROTO_SPEED_PSIE_SHIFT
| 10 << PROTO_SPEED_PSIM_SHIFT
| (Lp::SuperSpeedPlus as u32) << PROTO_SPEED_LP_SHIFT
| 5 << PROTO_SPEED_PSIV_SHIFT
),
// SuperSpeedPlus Gen1 x2
ProtocolSpeed::from_raw(
(Plt::Symmetric as u32) << PROTO_SPEED_PLT_SHIFT
| (true as u32) << PROTO_SPEED_PFD_SHIFT
| (Psie::Gbps as u32) << PROTO_SPEED_PSIE_SHIFT
| 10 << PROTO_SPEED_PSIM_SHIFT
| (Lp::SuperSpeedPlus as u32) << PROTO_SPEED_LP_SHIFT
| 6 << PROTO_SPEED_PSIV_SHIFT
),
// SuperSpeedPlus Gen2 x2
ProtocolSpeed::from_raw(
(Plt::Symmetric as u32) << PROTO_SPEED_PLT_SHIFT
| (true as u32) << PROTO_SPEED_PFD_SHIFT
| (Psie::Gbps as u32) << PROTO_SPEED_PSIE_SHIFT
| 20 << PROTO_SPEED_PSIM_SHIFT
| (Lp::SuperSpeedPlus as u32) << PROTO_SPEED_LP_SHIFT
| 7 << PROTO_SPEED_PSIV_SHIFT
),
];
let supp_proto = self.supported_protocols_iter().find(|supp_proto| supp_proto.compat_port_range().contains(&port))?;
Some(if supp_proto.psic() != 0 {
unsafe { supp_proto.protocol_speeds().iter() }
} else {
DEFAULT_SUPP_PROTO_SPEEDS.iter()
})
}
pub fn lookup_psiv(&self, port: u8, psiv: u8) -> Option<&'static ProtocolSpeed> {
self.supported_protocol_speeds(port)?.find(|speed| speed.psiv() == psiv)
}
}
#[derive(Deserialize)]
struct DriverConfig {
+4
View File
@@ -1,5 +1,9 @@
use std::slice;
use std::num::NonZeroU8;
use syscall::io::{Io, Mmio};
use super::CapabilityRegs;
#[repr(packed)]
pub struct OperationalRegs {
pub usb_cmd: Mmio<u32>,
+4 -4
View File
@@ -39,12 +39,12 @@ impl Port {
self.portsc.read()
}
pub fn state(&self) -> u32 {
(self.read() & (0b1111 << 5)) >> 5
pub fn state(&self) -> u8 {
((self.read() & (0b1111 << 5)) >> 5) as u8
}
pub fn speed(&self) -> u32 {
(self.read() & (0b1111 << 10)) >> 10
pub fn speed(&self) -> u8 {
((self.read() & (0b1111 << 10)) >> 10) as u8
}
pub fn flags(&self) -> PortFlags {
+5
View File
@@ -239,6 +239,11 @@ impl Xhci {
return Err(Error::new(EBADMSG));
}
let port_speed_id = self.ports[port].speed();
// FIXME
let speed_id = self.lookup_psiv(port as u8, port_speed_id);
dbg!(speed_id);
let port_state = self.port_states.get_mut(&port).ok_or(Error::new(ENOENT))?;
let input_context: &mut Dma<InputContext> = &mut port_state.input_context;