Make it possible to change KernelArgsAp without changing the trampolines

src/acpi/madt/arch/x86.rs

@@ -4,6 +4,8 @@ use core::{
 };
 
 use crate::{
+    arch::start::KernelArgsAp,
+    cpu_set::LogicalCpuId,
     device::local_apic::the_local_apic,
     memory::{allocate_p2frame, Frame, KernelMapper},
     paging::{Page, PageFlags, PhysicalAddress, RmmA, RmmArch, VirtualAddress, PAGE_SIZE},
@@ -70,19 +72,23 @@ pub(super) fn init(madt: Madt) {
                                 + crate::PHYS_OFFSET;
                             let stack_end = stack_start + (PAGE_SIZE << 4);
 
+                            let args = KernelArgsAp {
+                                cpu_id: LogicalCpuId::new(ap_local_apic.processor.into()),
+                                page_table: page_table_physaddr,
+                                stack_end: stack_end,
+                            };
+
                             let ap_ready = (TRAMPOLINE + 8) as *mut u64;
-                            let ap_cpu_id = unsafe { ap_ready.add(1) };
+                            let ap_args_ptr = unsafe { ap_ready.add(1) };
                             let ap_page_table = unsafe { ap_ready.add(2) };
-                            let ap_stack_start = unsafe { ap_ready.add(3) };
-                            let ap_stack_end = unsafe { ap_ready.add(4) };
-                            let ap_code = unsafe { ap_ready.add(5) };
+                            let ap_stack_end = unsafe { ap_ready.add(3) };
+                            let ap_code = unsafe { ap_ready.add(4) };
 
                             // Set the ap_ready to 0, volatile
                             unsafe {
                                 ap_ready.write(0);
-                                ap_cpu_id.write(ap_local_apic.processor.into());
+                                ap_args_ptr.write(&args as *const _ as u64);
                                 ap_page_table.write(page_table_physaddr as u64);
-                                ap_stack_start.write(stack_start as u64);
                                 ap_stack_end.write(stack_end as u64);
                                 ap_code.write(kstart_ap as u64);
 

src/arch/x86_shared/start.rs

@@ -221,14 +221,10 @@ pub unsafe extern "C" fn kstart(args_ptr: *const KernelArgs) -> ! {
     }
 }
 
-#[repr(C, packed)]
 pub struct KernelArgsAp {
-    // TODO: u32?
-    cpu_id: u64,
-
-    page_table: u64,
-    stack_start: u64,
-    stack_end: u64,
+    pub cpu_id: LogicalCpuId,
+    pub page_table: usize,
+    pub stack_end: usize,
 }
 
 /// Entry to rust for an AP
@@ -236,11 +232,6 @@ pub unsafe extern "C" fn kstart_ap(args_ptr: *const KernelArgsAp) -> ! {
     unsafe {
         let cpu_id = {
             let args = &*args_ptr;
-            let cpu_id = LogicalCpuId::new(args.cpu_id as u32);
-            let bsp_table = args.page_table as usize;
-            let _stack_start = args.stack_start as usize;
-            let stack_end = args.stack_end as usize;
-
             assert_eq!(BSS_TEST_ZERO.get().read(), 0);
             assert_eq!(DATA_TEST_NONZERO.get().read(), usize::max_value());
 
@@ -251,17 +242,17 @@ pub unsafe extern "C" fn kstart_ap(args_ptr: *const KernelArgsAp) -> ! {
             idt::init();
 
             // Initialize paging
-            RmmA::set_table(TableKind::Kernel, PhysicalAddress::new(bsp_table));
+            RmmA::set_table(TableKind::Kernel, PhysicalAddress::new(args.page_table));
             paging::init();
 
             // Set up GDT with TLS
-            gdt::init_paging(stack_end, cpu_id);
+            gdt::init_paging(args.stack_end, args.cpu_id);
 
             #[cfg(all(target_arch = "x86_64", feature = "profiling"))]
             crate::profiling::init();
 
             // Set up IDT for AP
-            idt::init_paging_post_heap(cpu_id);
+            idt::init_paging_post_heap(args.cpu_id);
 
             #[cfg(target_arch = "x86_64")]
             crate::alternative::early_init(false);
@@ -271,14 +262,14 @@ pub unsafe extern "C" fn kstart_ap(args_ptr: *const KernelArgsAp) -> ! {
 
             // Initialize miscellaneous processor features
             #[cfg(target_arch = "x86_64")]
-            crate::misc::init(cpu_id);
+            crate::misc::init(args.cpu_id);
 
             // Initialize devices (for AP)
             device::init_ap();
 
             AP_READY.store(true, Ordering::SeqCst);
 
-            cpu_id
+            args.cpu_id
         };
 
         while !BSP_READY.load(Ordering::SeqCst) {

src/asm/x86/trampoline.asm

@@ -9,9 +9,8 @@ trampoline:
     jmp short startup_ap
     times 8 - ($ - trampoline) nop
     .ready: dq 0
-    .cpu_id: dq 0
+    .args_ptr: dq 0
     .page_table: dq 0
-    .stack_start: dq 0
     .stack_end: dq 0
     .code: dq 0
 
@@ -72,7 +71,7 @@ protected_mode_ap:
     mov eax, [trampoline.stack_end]
     lea esp, [eax - 256]
 
-    mov eax, trampoline.cpu_id
+    mov eax, [trampoline.args_ptr]
     push eax
 
     mov eax, [trampoline.code]

src/asm/x86_64/trampoline.asm

@@ -9,9 +9,8 @@ trampoline:
     jmp short startup_ap
     times 8 - ($ - trampoline) nop
     .ready: dq 0
-    .cpu_id: dq 0
+    .args_ptr: dq 0
     .page_table: dq 0
-    .stack_start: dq 0
     .stack_end: dq 0
     .code: dq 0
 
@@ -79,7 +78,7 @@ long_mode_ap:
     mov rcx, [trampoline.stack_end]
     lea rsp, [rcx - 256]
 
-    mov rdi, trampoline.cpu_id
+    mov rdi, [trampoline.args_ptr]
 
     mov rax, [trampoline.code]
     mov qword [trampoline.ready], 1