usb: P2-B complete — HCCPARAMS2 capability gating in xhcid

Track base pointer to d20557f7 (xHCI 1.1+ feature gating: LEC/U3C/CIC
gates, HW LPM substrate with protocol-caps HLC detection, PORTPMSC
register-target fix, bogus HCCPARAMS1-HLC accessor removed).

Mark P2-B COMPLETE in USB-IMPLEMENTATION-PLAN.md with the full gating
inventory and Linux 7.1 cross-references. Per-device L1 enablement
(BESL, MEL Evaluate Context) explicitly deferred to P3 hub work.

local/docs/USB-IMPLEMENTATION-PLAN.md

@@ -204,24 +204,45 @@ None are stubs. Original plan incorrectly stated they were 32-line "not yet impl
 
 **Exit:** per-controller quirk probe running at init; quirk-aware behavior in 5+ paths.
 
-### P2-B: HCCPARAMS2 parsing (xHCI 1.1+ features)
+### P2-B: HCCPARAMS2 parsing (xHCI 1.1+ features) ✅ COMPLETE (2026-07-18)
 
 **Reference:** `local/reference/linux-7.1/drivers/usb/host/xhci-caps.h:94-119`
 
 13 HCCPARAMS2 bits enable U3 entry, extended TBC, eUSB2, etc. Current xhcid reads only HCCPARAMS1.
 
-**Tasks:**
+**Status:** Parsing was already complete (all 11 HCCPARAMS2 bit constants +
+accessors + HCS3 latencies in `capability.rs`). Gating implemented per Linux
+7.1 cross-reference:
 
-1. Read and cache `HCSPARAMS2` and `HCCPARAMS2` in `capability.rs`.
-2. Define bitflags for each of the 13 capabilities.
-3. Gate xHCI 1.1+ features on these bits:
-   - `HCC2_U3C` — U3 Entry Capability
-   - `HCC2_CMC` — Configure Endpoint Max Exit Latency Too Large
-   - `HCC2_LEC` — Large ESIT Payload (>48KB)
-   - `HCC2_CIC` — Configuration Information Capability (used for Set Latency Tolerance)
-4. Extended port capabilities from `xhci-ext-caps.h:62-66`: `XHCI_L1C`, `XHCI_HLC`, `XHCI_BLC` for LPM.
+1. **LEC gate (HCC2_LEC)** — `scheme.rs`: `lec = hci_ver > 0x100 && cap.lec()`
+   (Linux xhci-mem.c:1350 exact condition); gates isoch Mult field (existing
+   `isoch_mult(lec)`) and zeroes Max ESIT Payload Hi when LEC=0 (spec Table 6-8
+   RsvdZ requirement).
+2. **U3C gate (HCC2_U3C)** — `suspend_port()` refuses SS U3 entry with ENOSYS
+   when `hci_ver >= 0x110 && !hcc2_u3c()` (spec §4.15.1; Linux ignores the bit,
+   xhcid is spec-strict). USB2 suspend unaffected (bus-level suspended state).
+3. **CMC (HCC2_CMC)** — no active gate (mirrors Linux: error 0x1D
+   MaxExitLatencyTooLarge handled unconditionally via P2-C completion codes).
+4. **CIC (HCC2_CIC)** — already gated pre-existing: CONFIG.CIE set from
+   `cic()` (mod.rs), now with `hci_ver > 0x100` guard; CIE consumed in input
+   control context build (scheme.rs).
+5. **HW LPM (XHCI_HLC/BLC/L1C)** — new `SupportedProtoCap::{hw_lpm_capable,
+   besl_lpm_capable, l1_capable}` accessors (protocol-defined bits, Linux
+   xhci-ext-caps.h:62-66); `Xhci::hw_lpm_support` computed per Linux
+   xhci-mem.c:2137 (`hci_ver >= 0x100 && !HW_LPM_DISABLE && any USB2 protocol
+   cap has HLC`); defensive LPM clear on USB2 ports at attach when unsupported
+   (Linux xhci.c:4725 disable path); `Port::enable_lpm/disable_lpm` register
+   targets fixed (HLE/HIRD/RWE/L1DS belong in PORTPMSC, not PORTHLPMC —
+   spec Tables 5-21/5-23). Per-device L1 enablement (BESL computation, MEL
+   Evaluate Context) deferred to P3 hub work.
+6. **Bug fix:** removed bogus `CapabilityRegs::hlc()` + `HCC_PARAMS1_HLC_BIT`
+   (read xECP pointer bits, not HLC — HLC is in the protocol caps, not
+   HCCPARAMS1).
+7. **Version guards:** HCC2 log block + `set_cie` gated on `hci_ver > 0x100`
+   (HCCPARAMS2 register space is reserved on xHCI 1.0).
 
-**Exit:** HCCPARAMS2 parsed; 3+ features gated on it.
+**Exit met:** HCCPARAMS2 parsed; 4 features gated (LEC×2, U3C, CIC, HW LPM
+substrate). cargo check clean (138 warnings, -2 vs baseline), 43/43 tests pass.
 
 ### P2-C: Error recovery