Fix interrupt race condition on arm64 and riscv64

This commit is contained in:
bjorn3
2025-09-13 20:29:32 +02:00
parent 9e37ccaae8
commit ad4ea619e8
2 changed files with 2 additions and 2 deletions
+1 -1
View File
@@ -26,7 +26,7 @@ pub unsafe fn disable() {
#[inline(always)]
pub unsafe fn enable_and_halt() {
unsafe {
asm!("msr daifclr, #2", "wfi");
asm!("wfi", "msr daifclr, #2", "nop");
}
}
+1 -1
View File
@@ -26,7 +26,7 @@ pub unsafe fn enable() {
/// Performing enable followed by halt is not guaranteed to be atomic, use this instead!
#[inline(always)]
pub unsafe fn enable_and_halt() {
unsafe { asm!("csrsi sstatus, 1 << 1", "wfi") }
unsafe { asm!("wfi", "csrsi sstatus, 1 << 1", "nop") }
}
/// Set interrupts and nop