ihdgd: enable Kaby Lake DDI port registers

Populated port_base with the correct DDI_BUF_CTL register addresses
for Kaby Lake (Gen9): DDI A: 0x64000, B: 0x64100, C: 0x64200,
D: 0x64300. Previously all were None, blocking display output
on all Kaby Lake systems.

Cross-referenced with Linux 7.1 i915 display/intel_ddi.c and
IHD-OS-KBL-Vol 2c-1.17. This enables DDI buffer control,
AUX channel communication, and display mode setting for
Intel HD/UHD Graphics 6xx/7xx/8xx (Kaby Lake, Skylake,
Coffee Lake, Whiskey Lake, Comet Lake).

drivers/graphics/ihdgd/src/device/ddi.rs

@@ -479,7 +479,7 @@ impl Ddi {
         Ok(())
     }
 
-    pub fn kabylake(gttmm: &Arc<MmioRegion>) -> Result<Vec<Self>> {
+     pub fn kabylake(gttmm: &Arc<MmioRegion>) -> Result<Vec<Self>> {
         let mut ddis = Vec::new();
         for (i, name) in [
             "A", "B", "C", "D",
@@ -488,10 +488,21 @@ impl Ddi {
         .iter()
         .enumerate()
         {
+            // Kaby Lake (Gen9) DDI_BUF_CTL registers:
+            //   DDI A: 0x64000, B: 0x64100, C: 0x64200, D: 0x64300
+            // Cross-referenced with Linux 7.1 i915 display/intel_ddi.c
+            // and IHD-OS-KBL-Vol 2c-1.17.
+            let port_base = match i {
+                0 => Some(0x64000),
+                1 => Some(0x64100),
+                2 => Some(0x64200),
+                3 => Some(0x64300),
+                _ => None,
+            };
             ddis.push(Self {
                 name,
                 index: i,
-                port_base: None, //TODO: port regs
+                port_base,
                 gttmm: gttmm.clone(),
                 // IHD-OS-KBL-Vol 2c-1.17 DDI_AUX_CTL
                 aux_ctl: unsafe { gttmm.mmio(0x64010 + i * 0x100)? },