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Match ac97 and hda buffering

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This commit is contained in:
Jeremy Soller
2022-11-20 13:16:51 -07:00
parent c57b3c8910
commit 9315af5e41
2 changed files with 6 additions and 10 deletions
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ac97d/src/device.rs
+2 -2
View File
@@ -266,8 +266,8 @@ impl SchemeBlockMut for Ac97 {
let civ = self.bus.po.civ.read() as usize;
let mut lvi = self.bus.po.lvi.read() as usize;
if lvi == (civ + 1) % NUM_SUB_BUFFS {
// Block if we already are 1 buffer ahead
if lvi == (civ + 3) % NUM_SUB_BUFFS {
// Block if we already are 3 buffers ahead
Ok(None)
} else {
// Fill next buffer
ihdad/src/hda/device.rs
+4 -8
View File
@@ -55,7 +55,7 @@ const IRV: u16 = 1 << 1;
const COMMAND_BUFFER_OFFSET: usize = 0x40;
const NUM_SUB_BUFFS: usize = 4;
const NUM_SUB_BUFFS: usize = 32;
const SUB_BUFF_SIZE: usize = 2048;
enum Handle {
@@ -781,16 +781,12 @@ impl IntelHDA {
let os = self.output_streams.get_mut(index as usize).unwrap();
//let sample_size:usize = output.sample_size();
let mut open_block = (output.link_position() as usize) / os.block_size();
open_block += NUM_SUB_BUFFS / 2;
while open_block >= NUM_SUB_BUFFS {
open_block -= NUM_SUB_BUFFS;
}
let open_block = (output.link_position() as usize) / os.block_size();
//log::info!("Status: {:02X} Pos: {:08X} Output CTL: {:06X}", output.status(), output.link_position(), output.control());
if open_block == os.current_block() {
if os.current_block() == (open_block + 3) % NUM_SUB_BUFFS {
// Block if we already are 3 buffers ahead
Ok(None)
} else {
os.write_block(buf).map(|count| Some(count))